CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip. - Mounir Benabdenbi; Walid Maroufi; Meryem Marzouki (DATE, 2000)

Solving the I/O Bandwidth Problem in System on a Chip Testing. - Walid Maroufi; Mounir Benabdenbi; Meryem Marzouki (SBCCI, 2000)

Testing TAPed cores and wrapped cores with the same test access mechanism. - Mounir Benabdenbi; Walid Maroufi; Meryem Marzouki (DATE, 2001)

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. - Mounir Benabdenbi; Walid Maroufi; Meryem Marzouki (J. Electron. Test., 2002)

STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores. - Mounir Benabdenbi; Alain Greiner; François Pêcheux; Emmanuel Viaud; Matthieu Tuna (DATE, 2004)

MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation. - Alain Greiner; Frédéric Pétrot; M. Carrier; Mounir Benabdenbi; Roselyne Chotin-Avot; Raphaël Labayrade (ReCoSoC, 2006)

At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. - Matthieu Tuna; Mounir Benabdenbi; Alain Greiner (VTS, 2007)

On-line test and monitoring of multi-processor SoCs: A software-based approach. - Mounir Benabdenbi; François Pêcheux; Etienne Faure (LATW, 2009)

An in-memory monitoring database for self adaptive MP2SoCs. - Etienne Faure; Gabriel Marchesan Almeida; Mounir Benabdenbi; Pascal Benoit; Fabien Clermidy; François Pêcheux; Gilles Sassatelli; Lionel Torres (DASIP, 2010)

Fault tolerant communication in 3D integrated systems. - Vladimir Pasca; Lorena Anghel; Mounir Benabdenbi (DSN Workshops, 2010)

Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. - Vladimir Pasca; Lorena Anghel; Claudia Rusu; Mounir Benabdenbi (ETS, 2010)

Distributed online software monitoring of manycore architectures. - Etienne Faure; Mounir Benabdenbi; François Pêcheux (IOLTS, 2010)

Configurable serial fault-tolerant link for communication in 3D integrated systems. - Vladimir Pasca; Lorena Anghel; Claudia Rusu; Mounir Benabdenbi (IOLTS, 2010)

Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components. - Zhen Zhang; Alain Greiner; Mounir Benabdenbi (IOLTS, 2010)

Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis. - Vladimir Pasca; Lorena Anghel; Mounir Benabdenbi (LATW, 2011)

Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure. - Zhen Zhang; Dimitri Refauvelet; Alain Greiner; Mounir Benabdenbi; François Pêcheux (VTS, 2011)

Efficient link-level error resilience in 3D NoCs. - Vladimir Pasca; Saif-Ur Rehman; Lorena Anghel; Mounir Benabdenbi (DDECS, 2012)

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis. - Vladimir Pasca; Lorena Anghel; Mounir Benabdenbi (J. Electron. Test., 2012)

CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems. - Vladimir Pasca; Lorena Anghel; Michael Nicolaidis; Mounir Benabdenbi (J. Electron. Test., 2012)

BIST for logic and local interconnect resources in a novel mesh of cluster FPGA. - Saif-Ur Rehman; Mounir Benabdenbi; Lorena Anghel (DFTS, 2013)

A defect-tolerant cluster in a mesh SRAM-based FPGA. - Arwa Ben Dhia; Saif-Ur Rehman; Adrien Blanchardon; Lirida A. B. Naviner; Mounir Benabdenbi; Roselyne Chotin-Avot; Emna Amouri; Habib Mehrez; Zied Marrakchi (FPT, 2013)

Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. - Michael G. Dimopoulos; Yi Gang; Mounir Benabdenbi; Lorena Anghel; Nacer-Eddine Zergainoh; Michael Nicolaidis (IOLTS, 2013)

System on chip project: Integration of a Motion-JPEG video decoder. - Lorena Anghel; Mounir Benabdenbi; Frédéric Pétrot (EWME, 2014)

Cost-efficient of a cluster in a mesh SRAM-based FPGA. - Saif-Ur Rehman; Mounir Benabdenbi; Lorena Anghel (IOLTS, 2014)

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. - Saif-Ur Rehman; Adrien Blanchardon; Arwa Ben Dhia; Mounir Benabdenbi; Roselyne Chotin-Avot; Lirida A. B. Naviner; Lorena Anghel; Habib Mehrez; Emna Amouri; Zied Marrakchi (ISVLSI, 2014)

Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. - Michael G. Dimopoulos; Yi Gang; Lorena Anghel; Mounir Benabdenbi; Nacer-Eddine Zergainoh; Michael Nicolaidis (Microprocess. Microsystems, 2014)

On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures. - Zhen Zhang; Dimitri Refauvelet; Alain Greiner; Mounir Benabdenbi; François Pêcheux (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Application-independent testing of multilevel interconnect in mesh-based FPGAs. - Saif-Ur Rehman; Mounir Benabdenbi; Lorena Anghel (DTIS, 2015)

Test and Reliability in Approximate Computing. - Lorena Anghel; Mounir Benabdenbi; Alberto Bosio; Marcello Traiola; Elena-Ioana Vatajelu (J. Electron. Test., 2018)

On-Line Adjustable Precision Computing. - Ali Skaf; Mona Ezzadeen; Mounir Benabdenbi; Laurent Fesquet (DTIS, 2019)

FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach. - Noureddine Ait Said; Mounir Benabdenbi; Katell Morin-Allory (DTIS, 2020)

FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method. - Noureddine Ait Said; Mounir Benabdenbi; Katell Morin-Allory (ISVLSI, 2021)

Combining Acceleration and Approximation in Dependable Edge AI: Optimization Methodology and Tools Applied to a Case Study. - Régis Leveugle; Mounir Benabdenbi; Ahmed Al Kaf; Luc Noizette (DTTIS, 2024)