Very high speed integrated circuits for optical communication. - Agnieszka Konczykowska; Mounir Meghelli (ICECS, 1998)

InP DHBT technology and design methodology for high-bit-rate optical communications circuits. - Philippe André; Jean-Louis Benchimol; Patrick Desrousseaux; Anne-Marie Duchenois; Jean Godin; Agnieszka Konczykowska; Mounir Meghelli; Muriel Riet; André Scavennec (IEEE J. Solid State Circuits, 1998)

High power and high speed InP DHBT driver IC's for laser modulation. - Mounir Meghelli; Michel Bouché; Agnieszka Konczykowska (IEEE J. Solid State Circuits, 1998)

SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems. - Mounir Meghelli; Benjamin D. Parker; Herschel A. Ainspan; Mehmet Soyuer (IEEE J. Solid State Circuits, 2000)

Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits. - Mehmet Soyuer; Herschel A. Ainspan; Mounir Meghelli; Jean-Olivier Plouchart (Proc. IEEE, 2000)

40-Gb/s circuits built from a 120-GHz fT SiGe technology. - Greg G. Freeman; Mounir Meghelli; Young Kwark; Steven Zier; Alexander V. Rylyakov; Michael Sorna; Todd Tanji; Oswin M. Schreiber; Keith Walter; Jae-Sung Rieh; Basanth Jagannathan; Alvin J. Joseph; et al. (IEEE J. Solid State Circuits, 2002)

50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems. - Mounir Meghelli; Alexander V. Rylyakov; Lei Shan (IEEE J. Solid State Circuits, 2002)

45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. - Seongwon Kim; Mohit Kapur; Mounir Meghelli; Alexander V. Rylyakov; Young Hoon Kwark; Daniel J. Friedman (CICC, 2003)

SiGe BiCMOS integrated circuits for high-speed serial communication links. - Daniel J. Friedman; Mounir Meghelli; Benjamin D. Parker; Jungwook Yang; Herschel A. Ainspan; Alexander V. Rylyakov; Young Hoon Kwark; Mark B. Ritter; Lei Shan; Steven J. Zier; Michael Sorna; Mehmet Soyuer (IBM J. Res. Dev., 2003)

A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. - Mounir Meghelli; Alexander V. Rylyakov; Steven Zier; Michael Sorna; Daniel J. Friedman (IEEE J. Solid State Circuits, 2003)

132-Gb/s 4: 1 multiplexer in 0.13-μm SiGe-bipolar technology. - Mounir Meghelli (IEEE J. Solid State Circuits, 2004)

A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS. - Behnam Analui; Alexander V. Rylyakov; Sergey V. Rylov; Mounir Meghelli; Ali Hajimiri (IEEE J. Solid State Circuits, 2005)

A 43-Gb/s full-rate clock transmitter in 0.18-μm SiGe BiCMOS technology. - Mounir Meghelli (IEEE J. Solid State Circuits, 2005)

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. - Mounir Meghelli; Sergey V. Rylov; John F. Bulzacchelli; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; L. Shan; et al. (ISSCC, 2006)

Phase and amplitude pre-emphasis techniques for low-power serial links. - James F. Buckwalter; Mounir Meghelli; Daniel J. Friedman; Ali Hajimiri (IEEE J. Solid State Circuits, 2006)

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. - John F. Bulzacchelli; Mounir Meghelli; Sergey V. Rylov; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; Lei Shan; et al. (IEEE J. Solid State Circuits, 2006)

Introduction to the Special Section on the 2008 Compound Semiconductor Integrated Circuit Symposium (CSICS'08). - Mounir Meghelli; Robert Shimon (IEEE J. Solid State Circuits, 2008)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)

A linearized voltage-controlled oscillator for dual-path phase-locked loops. - Glenn E. R. Cowan; Mounir Meghelli; Daniel J. Friedman (ISCAS, 2013)

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Mounir Meghelli; Daniel J. Friedman (CICC, 2015)

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (ISSCC, 2015)

A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array. - Benjamin G. Lee; Renato Rimolo-Donadio; Alexander V. Rylyakov; Jonathan E. Proesel; John F. Bulzacchelli; Christian W. Baks; Mounir Meghelli; Clint L. Schow; Anand Ramaswamy; Jonathan E. Roth; Jae-Hyuk Shin; Brian R. Koch; et al. (OFC, 2015)

A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs. - Anand Ramaswamy; Jonathan E. Roth; Erik J. Norberg; Robert S. Guzzon; Jae-Hyuk Shin; J. T. Imamura; Brian R. Koch; Daniel K. Sparacin; Gregory A. Fish; Benjamin G. Lee; Renato Rimolo-Donadio; Christian W. Baks; et al. (OFC, 2015)

A 25 Gb/s burst-mode receiver for low latency photonic switch networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Clint Schow; Mounir Meghelli (OFC, 2015)

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (IEEE J. Solid State Circuits, 2015)

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. - Sergey V. Rylov; Troy J. Beukema; Zeynep Toprak Deniz; Thomas Toifl; Yong Liu 023; Ankur Agrawal; Peter Buchmann; Alexander V. Rylyakov; Michael P. Beakes; Benjamin D. Parker; Mounir Meghelli (ISSCC, 2016)

Monolithic silicon photonics at 25 Gb/s. - Jason S. Orcutt; Douglas M. Gill; Jonathan E. Proesel; John J. Ellis-Monaghan; Folkert Horst; Tymon Barwicz; Chi Xiong; Frederick G. Anderson; Ankur Agrawal; Yves Martin; Christian W. Baks; Marwan Khater; et al. (OFC, 2016)

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Michael P. Beakes; Mounir Meghelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2016)

Internet of the Body and Cognitive Hypervisor. - Rahel Strässle; Sebastian Gerke; Thomas Brunschwiler; Yuksel Temiz; Jonas R. M. Weiss; Arvind Sridhar; Stephan Paredes; Emanuel Loertscher; Neil Ebejer; Bruno Michel; H.-M. Lee; C. Alvarado; et al. (CHASE, 2017)

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. - Alessandro Cevrero; Ilter Özkaya; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; Benjamin G. Lee; et al. (ISSCC, 2017)

6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. - Timothy O. Dickson; Herschel A. Ainspan; Mounir Meghelli (ISSCC, 2017)

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Christian W. Baks; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; et al. (IEEE J. Solid State Circuits, 2017)

Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference. - Tim Piessens; Seung-Tak Ryu; Chih-Ming Hung; Alyosha C. Molnar; Mounir Meghelli (IEEE J. Solid State Circuits, 2017)

Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee. - Mounir Meghelli; Hyeon-Min Bae; Frank O'Mahony (ISSCC, 2018)

A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Thomas Morf; Daniel M. Kuchta; Lukas Kull; Marcel A. Kossel; Danny Luu; Mounir Meghelli; Yusuf Leblebici; et al. (ISSCC, 2018)

F5: Advanced optical communication: From devices, circuits, and architectures to algorithms. - Bo Zhang; Frederic Gianesello; Simone Erba; Mounir Meghelli; Azita Emami; Takayuki Shibasaki (ISSCC, 2018)

FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS. - Benjamin G. Lee; Nicolas Dupuis; Jason Orcutt; Javier Ayala; Karen Nummy; Herschel A. Ainspan; Jonathan E. Proesel; Christian W. Baks; Douglas M. Gill; Mounir Meghelli; William M. J. Green (OFC, 2018)

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Christian W. Baks; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; et al. (IEEE J. Solid State Circuits, 2018)

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. - Jonathan E. Proesel; Zeynep Toprak Deniz; Alessandro Cevrero; Ilter Özkaya; Seongwon Kim; Daniel M. Kuchta; Sungjae Lee 005; Sergey V. Rylov; Herschel A. Ainspan; Timothy O. Dickson; John F. Bulzacchelli; Mounir Meghelli (IEEE J. Solid State Circuits, 2018)

A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (ISSCC, 2019)

Multi-Wavelength Optical Transceivers Integrated on Node (MOTION). - Daniel M. Kuchta; Jonathan E. Proesel; Fuad E. Doany; Wooram Lee; Timothy O. Dickson; Herschel A. Ainspan; Mounir Meghelli; Petar K. Pepeljugoski; Xiaoxiong Gu; Michael P. Beakes; Mark Schultz; Marc Taubenblatt; et al. (OFC, 2019)

Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches. - Benjamin G. Lee; Nicolas Dupuis; Fuad E. Doany; Laurent Schares; Nicolas Boyer; Nathalie Normand; Herschel A. Ainspan; Christian W. Baks; Jonathan E. Proesel; Isabel De Sousa; Mounir Meghelli; Marc A. Taubenblatt (OFC, 2019)

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; John F. Bulzacchelli; Marcel A. Kossel; Pier Andrea Francese; Thomas Morf; Jonathan E. Proesel; Herschel A. Ainspan; Matthias Brändli; Mounir Meghelli (CICC, 2024)

A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1 mathrm{V}_{ text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. - Zeynep Toprak Deniz; Timothy O. Dickson; Martin Cochet; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Matthias Brändli; Thomas Morf; Michael P. Beakes; Mounir Meghelli (VLSI Technology and Circuits, 2024)