Controlling State Explosion in Static Simulation by Selective Composition. - Partha Pratim Chakrabarti; Pallab Dasgupta; Partha Pratim Das 001; Arnob Roy; Shuvendu K. Lahiri; Mrinal Bose (VLSI Design, 1999)

A genetic approach to automatic bias generation for biased random instruction generation. - Mrinal Bose; Jongshin Shin; Elizabeth M. Rudnick; Todd Dukes; Magdy Abadir (CEC, 2001)

Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. - Mrinal Bose; Elizabeth M. Rudnick; Magdy S. Abadir (IOLTW, 2001)

Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification. - Mrinal Bose; Mark H. Nodine; William R. Jurasz Jr.; Vlad Zavadsky; Arvind Chodavadia; Lincoln R. Nunes (MTV, 2003)

Accelerating multi-party scheduling for transaction-level modeling. - Di Wang; Vyas Venkataraman; Zhen Wang 001; Wei Qin; Hangsheng Wang; Mrinal Bose; Jayanta Bhadra (ACM Great Lakes Symposium on VLSI, 2009)

An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. - Mrinal Bose; Prashant Naphade; Jayanta Bhadra; Hillel Miller (ISQED, 2009)

Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models. - Vyas Venkataraman; Di Wang; Atabak Mahram; Wei Qin; Mrinal Bose; Jayanta Bhadra (ISVLSI, 2009)

Portable simulation/emulation stimulus on an industrial-strength SoC. - Francisco Torres; Rohit Srivastava; Javier Ruiz; Charles H.-P. Wen; Mrinal Bose; Jayanta Bhadra (ITC, 2009)

Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling. - Vyas Venkataraman; Di Wang; Wei Qin; Mrinal Bose; Jayanta Bhadra (MTV, 2009)