A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator. - Mu-Chen Huang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing. - Mu-Chen Huang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application. - Chen-Yen Ho; Zwei-Mei Lee; Mu-Chen Huang; Sheng-Jui Huang (A-SSCC, 2011)

A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC. - Chun-Cheng Liu; Mu-Chen Huang; Yu-Hsuan Tu (IEEE J. Solid State Circuits, 2016)

28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter. - Chun-Cheng Liu; Mu-Chen Huang (ISSCC, 2017)