A 65nm low power 2T1D embedded DRAM with leakage current reduction. - Mu-Tien Chang; Po-Tsang Huang; Wei Hwang (SoCC, 2007)

A fully-differential subthreshold SRAM cell with auto-compensation. - Mu-Tien Chang; Wei Hwang (APCCAS, 2008)

A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. - Mu-Tien Chang; Po-Tsang Huang; Wei Hwang (SoCC, 2008)

An analytical model to estimate PCM failure probability due to process variations. - Mu-Tien Chang; Bruce L. Jacob (SoCC, 2011)

Energy-Efficient Cached DIMM Architecture. - Mu-Tien Chang; Joe Gross; Bruce L. Jacob (MASCOTS, 2012)

Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. - Mu-Tien Chang; Paul Rosenfeld; Shih-Lien Lu; Bruce L. Jacob (HPCA, 2013)

Technology Implications for Large Last-Level Caches. - Mu-Tien Chang (2013)

FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration. - Krishna T. Malladi; Mu-Tien Chang; John Ping; Hongzhong Zheng (MASCOTS, 2015)

DRAM Refresh Mechanisms, Penalties, and Trade-Offs. - Ishwar Bhati; Mu-Tien Chang; Zeshan Chishti; Shih-Lien Lu; Bruce L. Jacob (IEEE Trans. Computers, 2016)

FlashStorageSim: Performance Modeling for SSD Architectures. - Krishna T. Malladi; Mu-Tien Chang; Dimin Niu; Hongzhong Zheng (NAS, 2017)

Architecting HBM as a high bandwidth, high capacity, self-managed last-level cache. - Tyler Stocksdale; Mu-Tien Chang; Hongzhong Zheng; Frank Mueller 001 (PDSW-DISCS@SC, 2017)

Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach. - Mu-Tien Chang; I. Stephen Choi; Dimin Niu; Hongzhong Zheng (ACM Great Lakes Symposium on VLSI, 2018)