Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. - Umut Arslan; Mark P. McCartney; Mudit Bhargava; Xin Li 001; Ken Mai; Lawrence T. Pileggi (CICC, 2008)

Low-overhead, digital offset compensated, SRAM sense amplifiers. - Mudit Bhargava; Mark P. McCartney; Alexander Hoefler; Ken Mai (CICC, 2009)

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. - Satyanand Nalam; Mudit Bhargava; Kyle Ringgenberg; Ken Mai; Benton H. Calhoun (ICCD, 2009)

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. - Satyanand Nalam; Mudit Bhargava; Ken Mai; Benton H. Calhoun (DAC, 2010)

Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses. - Mudit Bhargava; Cagla Cakir; Ken Mai (HOST, 2010)

Side-channel Attack Resistant ROM-based AES S-Box. - Craig Teegarden; Mudit Bhargava; Ken Mai (HOST, 2010)

FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). - Yu Cai 001; Erich F. Haratsch; Mark P. McCartney; Mudit Bhargava; Ken Mai (FPGA, 2011)

Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS. - Mudit Bhargava; Cagla Cakir; Ken Mai (CICC, 2012)

6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS. - Cagla Cakir; Mudit Bhargava; Ken Mai (CICC, 2012)

Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS. - Mudit Bhargava; Cagla Cakir; Ken Mai (HOST, 2012)

Stylometric Analysis for Authorship Attribution on Twitter. - Mudit Bhargava; Pulkit Mehndiratta; Krishna Asawa (BDA, 2013)

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. - Ben Niewenhuis; Ronald D. Blanton; Mudit Bhargava; Ken Mai (ITC, 2013)

Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. - Jangwoo Kim; Hyunggyun Yang; Mark P. McCartney; Mudit Bhargava; Ken Mai; Babak Falsafi (PRDC, 2013)

Reliable, Secure, Efficient Physical Unclonable Functions. - Mudit Bhargava (2013)

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. - Mudit Bhargava; Ken Mai (DATE, 2014)

Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques. - Mudit Bhargava; Y. K. Chong; Vincent Schuppe; Bikas Maiti; Martin Kinkade; Hsin-Yu Chen; Andy W. Chen; Sanjay Mangal; Jacek Wiatrowski; Gerald Gouya; Abhishek Baradia; Sriram Thyagarajan; et al. (VLSIC, 2014)

Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers. - Mudit Bhargava; Kaship Sheikh; Ken Mai (HOST, 2015)

Deeply hardware-entangled reconfigurable logic and interconnect. - Burak Erbagci; Mudit Bhargava; Rachel Dondero; Ken Mai (ReConFig, 2015)

A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. - Mudit Bhargava; Ken Mai (IACR Cryptol. ePrint Arch., 2015)

On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators. - Haitong Li; Mudit Bhargava; Paul N. Whatmough; H.-S. Philip Wong (DAC, 2019)

Enhanced 3D Implementation of an Arm® Cortex®-A Microprocessor. - Xiaoqing Xu; Mudit Bhargava; Steve Moore; Saurabh Sinha; Brian Cline (ISLPED, 2019)

A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms. - Cagla Cakir; Andy W. Chen; Y. K. Chong; Sriram Thyagarajan; Mark P. McCartney; Peixuan Tan; Yulin Shi; Mudit Bhargava (VLSI Circuits, 2019)

Secure hardware-entangled field programmable gate arrays. - Burak Erbagci; Nail Etkin Can Akkaya; Mudit Bhargava; Rachel Dondero; Ken Mai (J. Parallel Distributed Comput., 2019)

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. - Saurabh Sinha; Xiaoqing Xu; Mudit Bhargava; Shidhartha Das; Brian Cline; Greg Yeric (CoRR, 2020)

3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. - Rahul Mathur; Mudit Bhargava; Heath Perry; Alberto Cestero; Frank Frederick; Shawn Hung; Chien-Ju Chao; Daniel Smith; Daniel Fisher; Norman Robson; Xiaoqing Xu; Pranavi Chandupatla; et al. (CICC, 2021)

A Fokker-Planck Solver to Model MTJ Stochasticity. - Fernando García-Redondo; Pranay Prabhat; Mudit Bhargava (ESSDERC, 2021)

A Compact Model for Scalable MTJ Simulation. - Fernando García-Redondo; Pranay Prabhat; Mudit Bhargava; Cyrille Dray (CoRR, 2021)

A survey of Digital Manufacturing Hardware and Software Trojans. - Prithwish Basu Roy; Mudit Bhargava; Chia-Yun Chang; Ellen Hui; Nikhil Gupta 002; Ramesh Karri; Hammond Pearce (CoRR, 2023)