One-Level Cache Memory Design for Scalable SMT Architectures. - Muhamed F. Mudawar; John R. Wani (PDCS, 2004)

Scalable cache memory design for large-scale SMT architectures. - Muhamed F. Mudawar (WMPI, 2004)

A Locked Cache-based Synchronization Protocol for CMP. - Ihab Ismail; Khaled El-Ayat; Muhamed F. Mudawar (PDPTA, 2006)

Efficient Generation of Compact Execution Traces for Multicore Architectural Simulations. - Ayman Hroub; Muhammad E. S. Elrabaa; Muhamed F. Mudawar; Ahmad Khayyat (ACM Trans. Archit. Code Optim., 2017)

A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations. - Muhammad E. S. Elrabaa; Ayman Hroub; Muhamed F. Mudawar; Amran Al-Aghbari; Mohammed Alasli; Ahmad Khayyat (IEEE Trans. Parallel Distributed Syst., 2017)

Exact Versus Inexact Decimal Floating-Point Numbers and Arithmetic. - Muhamed F. Mudawar (IEEE Access, 2023)

Accelerating memory and I/O intensive HPC applications using hardware compression. - Saleh Alsaleh; Muhammad E. S. Elrabaa; Aiman El-Maleh; Khaled A. Daud; Ayman Hroub; Muhamed F. Mudawar; Thierry Tonellot (J. Parallel Distributed Comput., 2024)