A digital array based bit serial processor for arbitrary window size kernel convolution in vision sensors. - Mehdi Habibi; Alireza Bafandeh; Muhammad Ali Montazerolghaem (Integr., 2014)

A Predetermined LMS Digital Background Calibration Technique for Pipelined ADCs. - Muhammad Ali Montazerolghaem; Tohid Moosazadeh; Mohammad Yavari (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs. - Mohammad Ali Montazerolghaem; Tohid Moosazadeh; Mohammad Yavari (IEEE Trans. Very Large Scale Integr. Syst., 2017)

6.5 A 3dB-NF 160MHz-RF-BW Blocker-Tolerant Receiver with Third-Order Filtering for 5G NR Applications. - Mohammad Ali Montazerolghaem; Sergio Pires; Leo C. N. de Vreede; Masoud Babaie (ISSCC, 2021)

A 0.5-3GHz Receiver with a Parallel Preselect Filter Achieving 120dB/dec Channel Selectivity and +28dBm Out-of-Band IIP3. - Muhammad Ali Montazerolghaem; Leo C. N. de Vreede; Masoud Babaie (CICC, 2022)

A 300MHz-BW, 27-to-38dBm In-Band OIP3 sub-7GHz Receiver for 5G Local Area Base Station Applications. - Mohammad Ali Montazerolghaem; Leo C. N. de Vreede; Masoud Babaie (ISSCC, 2023)

A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station Applications. - Mohammad Ali Montazerolghaem; Leo C. N. de Vreede; Masoud Babaie (IEEE J. Solid State Circuits, 2023)

29.3 A Cryo-CMOS Receiver with 15K Noise Temperature Achieving 9.8dB SNR in 10μs Integration Time for Spin Qubit Readout. - Bagas Prabowo; Oriol Pietx-Casas; Mohammad Ali Montazerolghaem; Giordano Scappucci; Lieven M. K. Vandersypen; Fabio Sebastiano; Masoud Babaie (ISSCC, 2024)

A Highly Selective Receiver With Programmable Zeros and Second-Order TIA. - Mohammad Ali Montazerolghaem; Leo C. N. de Vreede; Masoud Babaie (IEEE J. Solid State Circuits, 2024)