Guided lightweight Software test qualification for IP integration using Virtual Prototypes. - Daniel Große; Hoang M. Le; Muhammad Hassan 002; Rolf Drechsler (ICCD, 2016)

Data flow testing for virtual prototypes. - Muhammad Hassan 002; Vladimir Herdt; Hoang M. Le; Mingsong Chen 001; Daniel Große; Rolf Drechsler (DATE, 2017)

Early SoC security validation by VP-based static information flow analysis. - Muhammad Hassan 002; Vladimir Herdt; Hoang M. Le; Daniel Große; Rolf Drechsler (ICCAD, 2017)

Testbench qualification for SystemC-AMS timed data flow models. - Muhammad Hassan 002; Daniel Große; Hoang M. Le; Thilo Vörtler; Karsten Einwich; Rolf Drechsler (DATE, 2018)

Data Flow Testing for SystemC-AMS Timed Data Flow Models. - Muhammad Hassan 002; Daniel Große; Hoang M. Le; Rolf Drechsler (DATE, 2019)

Functional Coverage-Driven Characterization of RF Amplifiers. - Muhammad Hassan 002; Daniel Große; Thilo Vörtler; Karsten Einwich; Rolf Drechsler (FDL, 2019)

Automated Analysis of Virtual Prototypes at Electronic System Level. - Mehran Goli; Muhammad Hassan 002; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2019)

Security validation of VP-based SoCs using dynamic information flow tracking. - Mehran Goli; Muhammad Hassan 002; Daniel Große; Rolf Drechsler (it Inf. Technol., 2019)

System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. - Muhammad Hassan 002; Daniel Große; Rolf Drechsler (ASP-DAC, 2021)

System Level Verification of Phase-Locked Loop using Metamorphic Relations. - Muhammad Hassan 002; Daniel Große; Rolf Drechsler (DATE, 2021)

Enhanced modern virtual prototype based verification flow for heterogeneous systems. - Muhammad Hassan 002 (2021)

Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters. - Kemal Çaglar Coskun; Muhammad Hassan 002; Rolf Drechsler (DDECS, 2022)

Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. - Arighna Deb; Kamalika Datta; Muhammad Hassan 002; Saeideh Shirinzadeh; Rolf Drechsler (ASP-DAC, 2023)

Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits. - Kemal Çaglar Coskun; Muhammad Hassan 002; Rolf Drechsler (DATE, 2023)

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. - Jens Trommer; Niladri Bhattacharjee; Thomas Mikolajick; Sebastian Huhn 001; Marcel Merten; Mohammed E. Djeridane; Muhammad Hassan 002; Rolf Drechsler; Shubham Rai; Nima Kavand; Armin Darjani; Akash Kumar 001; et al. (DATE, 2023)

Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques. - Marcel Merten; Muhammad Hassan 002; Rolf Drechsler (DDECS, 2023)

Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors. - Weiyan Zhang; Mehran Goli; Muhammad Hassan 002; Rolf Drechsler (DSD, 2023)

VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking. - Ece Nur Demirhan Coskun; Muhammad Hassan 002; Mehran Goli; Rolf Drechsler (ISQED, 2023)

Security Coverage Metrics for Information Flow at the System Level. - Ece Nur Demirhan Coskun; Sallar Ahmadi-Pour; Muhammad Hassan 002; Rolf Drechsler (ASPDAC, 2024)

LLMs for Hardware Verification: Frameworks, Techniques, and Future Directions. - Khushboo Qayyum; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Muhammad Hassan 002; Rolf Drechsler (ATS, 2024)

Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. - Kemal Çaglar Coskun; Muhammad Hassan 002; Lars Hedrich; Rolf Drechsler (DAC, 2024)

Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. - Khushboo Qayyum; Muhammad Hassan 002; Sallar Ahmadi-Pour; Chandan Kumar Jha 001; Rolf Drechsler (DAC, 2024)

LLM-Guided Formal Verification Coupled with Mutation Testing. - Muhammad Hassan 002; Sallar Ahmadi-Pour; Khushboo Qayyum; Chandan Kumar Jha 001; Rolf Drechsler (DATE, 2024)

Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification. - Khushboo Qayyum; Abhoy Kole; Kamalika Datta; Muhammad Hassan 002; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2024)

cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits. - Chandan Kumar Jha 001; Muhammad Hassan 002; Rolf Drechsler (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. - Chandan Kumar Jha 001; Khushboo Qayyum; Kemal Çaglar Coskun; Simranjeet Singh; Muhammad Hassan 002; Rainer Leupers; Farhad Merchant; Rolf Drechsler (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars. - Kousik Bhunia; Arighna Deb; Kamalika Datta; Muhammad Hassan 002; Saeideh Shirinzadeh; Rolf Drechsler (ACM Trans. Embed. Comput. Syst., 2024)

Prompt. Verify. Repeat. LLMs in the Hardware Verification Cycle. - Muhammad Hassan 002; Mohamed A. Nadeem; Khushboo Qayyum; Chandan Kumar Jha 001; Rolf Drechsler (COINS, 2025)

LLM-assisted Performance Estimation of Embedded Software on RISC-V Processors. - Weiyan Zhang; Muhammad Hassan 002; Rolf Drechsler (DDECS, 2025)

Formal Verification of Error Bounds for Resistive-Switching-Based Multilevel Matrix-Vector Multipliers. - Kemal Çaglar Coskun; Chandan Kumar Jha 001; Muhammad Hassan 002; Rolf Drechsler (ISQED, 2025)

Correct and Verify - CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders With Correct Carry Bits. - Chandan Kumar Jha 001; Khushboo Qayyum; Muhammad Hassan 002; Rolf Drechsler (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)