Minimizing FPGA Interconnect Delays. - Stephen Brown 003; Muhammad M. Khellah; Zvonko G. Vranesic (IEEE Des. Test Comput., 1996)

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. - Stephen Brown 003; Muhammad M. Khellah; Guy Lemieux (VLSI Design, 1996)

A Low-Power High-Performance Embedded SRAM Macrocell. - Amr M. Fahim; Muhammad M. Khellah; Mohamed I. Elmasry (Great Lakes Symposium on VLSI, 1998)

Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation. - Muhammad M. Khellah; Mohamed I. Elmasry (Great Lakes Symposium on VLSI, 1998)

A low-power high-performance current-mode multiport SRAM. - Muhammad M. Khellah; Mohamed I. Elmasry (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. - Yibin Ye; Muhammad M. Khellah; Dinesh Somasekhar; Ali Farhang; Vivek De (IEEE J. Solid State Circuits, 2003)

Variations-aware low-power design with voltage scaling. - Navid Azizi; Muhammad M. Khellah; Vivek De; Farid N. Najm (DAC, 2005)

A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. - Muhammad M. Khellah; Maged Ghoneima; James W. Tschanz; Yibin Ye; Nasser A. Kurd; Javed Barkatullah; Srikanth Nimmagadda; Yehea I. Ismail (ICCD, 2005)

Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. - Yehea I. Ismail; Muhammad M. Khellah; Maged Ghoneima; James W. Tschanz; Yibin Ye; Vivek De (ISCAS (1), 2005)

Reducing the data switching activity of serialized datastreams. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; Vivek De (ISCAS, 2006)

Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. - Yibin Ye; Muhammad M. Khellah; Dinesh Somasekhar; Vivek De (ISCAS, 2006)

Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. - Keith A. Bowman; James W. Tschanz; Muhammad M. Khellah; Maged Ghoneima; Yehea I. Ismail; Vivek De (ISLPED, 2006)

Reducing the Data Switching Activity on Serial Link Buses. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; Vivek De (ISQED, 2006)

A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. - Muhammad M. Khellah; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Yibin Ye; James W. Tschanz; Dinesh Somasekhar; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; Kevin Zhang 001; et al. (ISSCC, 2006)

Formal derivation of optimal active shielding for low-power on-chip buses. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; James W. Tschanz; Vivek De (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; James W. Tschanz; Vivek De (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. - Muhammad M. Khellah; Dinesh Somasekhar; Yibin Ye; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Murad Sunna; James W. Tschanz; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; et al. (IEEE J. Solid State Circuits, 2007)

Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. - Navid Azizi; Muhammad M. Khellah; Vivek De; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; Vivek De (VLSI Design, 2007)

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. - Chris Wilkerson; Hongliang Gao; Alaa R. Alameldeen; Zeshan Chishti; Muhammad M. Khellah; Shih-Lien Lu (ISCA, 2008)

Analytical Model for the Propagation Delay of Through Silicon Vias. - DiaaEldin Khalil; Yehea I. Ismail; Muhammad M. Khellah; Tanay Karnik; Vivek De (ISQED, 2008)

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Y. Borkar; Vivek De; Ali Keshavarzi (ISSCC, 2008)

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. - Maged Ghoneima; Muhammad M. Khellah; James W. Tschanz; Yibin Ye; Nasser A. Kurd; Javed Barkatullah; Srikanth Nimmagadda; Yehea I. Ismail; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Accurate Estimation of SRAM Dynamic Stability. - D. E. Khalil; Muhammad M. Khellah; Nam-Sung Kim; Yehea I. Ismail; Tanay Karnik; Vivek K. De (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. - Muhammad M. Khellah; Nam-Sung Kim; Yibin Ye; Dinesh Somasekhar; Tanay Karnik; Nitin Borkar; Gunjan Pandya; Fatih Hamzaoglu; Tom Coan; Yih Wang; Kevin Zhang 001; Clair Webb; et al. (IEEE J. Solid State Circuits, 2009)

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Borkar; Vivek K. De; Ali Keshavarzi (IEEE J. Solid State Circuits, 2009)

Trading Off Cache Capacity for Low-Voltage Operation. - Chris Wilkerson; Hongliang Gao; Alaa R. Alameldeen; Zeshan Chishti; Muhammad M. Khellah; Shih-Lien Lu (IEEE Micro, 2009)

SRAM dynamic stability estimation using MPFP and its applications. - DiaaEldin Khalil; Muhammad M. Khellah; Nam-Sung Kim; Yehea I. Ismail; Tanay Karnik; Vivek De (Microelectron. J., 2009)

SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; Vivek De (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Serial-Link Bus: A Low-Power On-Chip Bus Architecture. - Maged Ghoneima; Yehea I. Ismail; Muhammad M. Khellah; James W. Tschanz; Vivek De (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Resilient design in scaled CMOS for energy efficiency. - James W. Tschanz; Keith A. Bowman; Muhammad M. Khellah; Chris Wilkerson; Bibiche M. Geuskens; Dinesh Somasekhar; Arijit Raychowdhury; Jaydeep Kulkarni; Carlos Tokunaga; Shih-Lien Lu; Tanay Karnik; Vivek De (ASP-DAC, 2010)

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek De (CICC, 2010)

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. - Bibiche M. Geuskens; Muhammad M. Khellah; Jaydeep Kulkarni; Tanay Karnik; Vivek De (CICC, 2010)

Resilient microprocessor design for high performance & energy efficiency. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISLPED, 2010)

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. - Arijit Raychowdhury; Bibiche M. Geuskens; Jaydeep Kulkarni; James W. Tschanz; Keith A. Bowman; Tanay Karnik; Shih-Lien Lu; Vivek De; Muhammad M. Khellah (ISSCC, 2010)

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. - James W. Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISSCC, 2010)

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. - Dinesh Somasekhar; Balaji Srinivasan; Gunjan Pandya; Fatih Hamzaoglu; Muhammad M. Khellah; Tanay Karnik; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2010)

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. - Arijit Raychowdhury; Jim Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek K. De (IEEE J. Solid State Circuits, 2011)

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. - Arijit Raychowdhury; Bibiche M. Geuskens; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Tanay Karnik; Muhammad M. Khellah; Vivek K. De (IEEE J. Solid State Circuits, 2011)

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Characterization of Inverse Temperature Dependence in logic circuits. - Minki Cho; Muhammad M. Khellah; Kwanyeob Chae; Khondker Zakir Ahmed 001; James W. Tschanz; Saibal Mukhopadhyay (CICC, 2012)

Design for test and reliability in ultimate CMOS. - Michael Nicolaidis; Lorena Anghel; Nacer-Eddine Zergainoh; Yervant Zorian; Tanay Karnik; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Carlos Tokunaga; Arijit Raychowdhury; Muhammad M. Khellah; Jaydeep Kulkarni; et al. (DATE, 2012)

Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. - Jaydeep Kulkarni; Bibiche M. Geuskens; Tanay Karnik; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2012)

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. - Carlos Tokunaga; Joseph F. Ryan 002; Charles Augustine; Jaydeep P. Kulkarni; Yi-Chun Shih; Stephen T. Kim; Rinkle Jain; Keith A. Bowman; Arijit Raychowdhury; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2014)

A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. - Rinkle Jain; Bibiche M. Geuskens; Stephen T. Kim; Muhammad M. Khellah; Jaydeep Kulkarni; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2014)

Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS. - Minki Cho; Carlos Tokunaga; Muhammad M. Khellah; James W. Tschanz; Vivek De (CICC, 2015)

Designing low-VTh STT-RAM for write energy reduction in scaled technologies. - Farah B. Yahya; Mohammad M. Mansour; James W. Tschanz; Muhammad M. Khellah (ISQED, 2015)

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (ISSCC, 2015)

A fully integrated charge sharing active decap scheme for power supply noise suppression. - Ahmed M. Ammar; Rafik Guindi; Ethan Shih; Carlos Tokunaga; Jim Tschanz; Muhammad M. Khellah (SoCC, 2015)

Synaptic sampling in hardware spiking neural networks. - Sadique Sheik; Somnath Paul; Charles Augustine; Chinnikrishna Kothapalli; Muhammad M. Khellah; Gert Cauwenberghs; Emre Neftci (ISCAS, 2016)

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. - Minki Cho; Stephen T. Kim; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (ISSCC, 2016)

Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. - Minki Cho; Carlos Tokunaga; Stephen T. Kim; James W. Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2016)

Recap of the 2016 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2016). - Vijay Raghunathan; Muhammad M. Khellah (IEEE Des. Test, 2016)

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (IEEE J. Solid State Circuits, 2016)

Session 5 - Memory for emerging applications. - Muhammad M. Khellah; Rajiv V. Joshi (CICC, 2017)

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. - Minki Cho; Stephen T. Kim; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (IEEE J. Solid State Circuits, 2017)

Session 2 overview: Processors: Digital architectures and systems subcommittee. - Thomas Burd; Muhammad M. Khellah; Byeong-Gyu Nam (ISSCC, 2018)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference. - Keith A. Bowman; Muhammad M. Khellah; Takashi Kono; Joseph Shor; Pui-In Mak (IEEE J. Solid State Circuits, 2018)

An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop. - Suyoung Bang; Minki Cho; Pascal Meinerzhagen; Andres Malavasi; Muhammad M. Khellah; James W. Tschanz; Vivek De (ESSCIRC, 2019)

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. - Pascal Andreas Meinerzhagen; Sandip Kundu; Andres Malavasi; Trang Nguyen; Muhammad M. Khellah; James W. Tschanz; Vivek De (ESSCIRC, 2019)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. - Suyoung Bang; Wootaek Lim; Charles Augustine; Andres Malavasi; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2020)

2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. - Charles Augustine; Somnath Paul; Turbo Majumder; James W. Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2020)

Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. - Jaydeep P. Kulkarni; Andres Malavasi; Charles Augustine; Carlos Tokunaga; Jim Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2020)

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. - Somnath Paul; Turbo Majumder; Charles Augustine; Andres F. Malavasi; S. Usirikayala; Raghavan Kumar; Jisna Kollikunnel; S. Chhabra; Satish Yada; M. L. Barajas; Carlos Ornelas; Dan Lake; et al. (VLSI Circuits, 2020)

An All-Digital, $V_{ mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop. - Suyoung Bang; Minki Cho; Pascal Andreas Meinerzhagen; Andres Malavasi; Muhammad M. Khellah; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2020)

All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP. - Charles Augustine; A. Afzal; U. Misgar; Abdullah A. Owahid; A. Raman; K. Subramanian; Feroze Merchant; James W. Tschanz; Muhammad M. Khellah (VLSI Circuits, 2021)

Advances in Microprocessor Cache Architectures Over the Last 25 Years. - Ravi R. Iyer 001; Vivek De; Ramesh Illikkal; David A. Koufaty; Bhushan Chitlur; Andrew Herdrich; Muhammad M. Khellah; Fatih Hamzaoglu; Eric Karl (IEEE Micro, 2021)

A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. - Saurabh Kumar 003; Minki Cho; Luke R. Everson; Andres Malavasi; Dan Lake; Carlos Tokunaga; Muhammad M. Khellah; James W. Tschanz; Vivek De; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. - Charles Augustine; Pascal Meinerzhagen; Wootaek Lim; A. Veerabathini; M. Bright; K. Mojjada; Jim Tschanz; Muhammad M. Khellah; Vivek De (VLSI Technology and Circuits, 2023)