Current and future 3D activities at Fraunhofer. - Andy Heinig; Muhammad Waqas Chaudhary; Peter Schneider; Peter Ramm; Josef Weber (3DIC, 2015)

Interposer based integration to achieve high speed interfaces for ADC application. - Muhammad Waqas Chaudhary; Andy Heinig; Michael Dittrich (3DIC, 2016)

Co-design of CML IO and Interposer channel for low area and power signaling. - Muhammad Waqas Chaudhary; Andy Heinig (DDECS, 2016)

Interconnect Aware Power Optimization of Low Swing Driver for Multi-Chip Interfaces. - Muhammad Waqas Chaudhary; Andy Heinig; Bhaskar Choubey (ICECS, 2020)

13-Gb/s Transmitter for Bunch of Wires Chip-to-Chip Interface Standard. - Muhammad Waqas Chaudhary; Andy Heinig; Bhaskar Choubey (MWSCAS, 2020)

Transmitter and channel design for multi-chip communication interfaces (Sender und Kanaldesign für Multi-Chip-Kommunikationsschnittstellen) - Muhammad Waqas Chaudhary (2020)