A BiCMOS Operational Amplifier Achieving 0.33μV°C Offset Drift using Room-Temperature Trimming. - Muhammed Bolatkale; Michiel A. P. Pertijs; Wilko J. Kindt; Johan H. Huijsing; Kofi A. A. Makinwa (ISSCC, 2008)

A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW. - Muhammed Bolatkale; Lucien J. Breems; Robert Rutten; Kofi A. A. Makinwa (ISSCC, 2011)

A 4 GHz Continuous-Time ΔΣ ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW. - Muhammed Bolatkale; Lucien J. Breems; Robert Rutten; Kofi A. A. Makinwa (IEEE J. Solid State Circuits, 2011)

A Single-Temperature Trimming Technique for MOS-Input Operational Amplifiers Achieving 0.33 μ V/°C Offset Drift. - Muhammed Bolatkale; Michiel A. P. Pertijs; Wilko J. Kindt; Johan H. Huijsing; Kofi A. A. Makinwa (IEEE J. Solid State Circuits, 2011)

A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements. - Chenming Zhang; Lucien J. Breems; Georgi I. Radulov; Muhammed Bolatkale; Hans Hegt; Arthur H. M. van Roermund (ISCAS, 2016)

15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW. - Lucien J. Breems; Muhammed Bolatkale; Hans Brekelmans; Shagun Bajoria; Jan Niehof; Robert Rutten; Bert Oude-Essink; Franco Fritschij; Jagdip Singh; Gerard Lassche (ISSCC, 2016)

A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth. - Lucien J. Breems; Muhammed Bolatkale; Hans Brekelmans; Shagun Bajoria; Jan Niehof; Robert Rutten; Bert Oude-Essink; Franco Fritschij; Jagdip Singh; Gerard Lassche (IEEE J. Solid State Circuits, 2016)

A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator. - Pierluigi Cenci; Muhammed Bolatkale; Robert Rutten; Gerard Lassche; Kofi A. A. Makinwa; Lucien J. Breems (ESSCIRC, 2017)

Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. - Chenming Zhang; Lucien J. Breems; Georgi I. Radulov; Muhammed Bolatkale; Qilong Liu; Hans Hegt; Arthur H. M. van Roermund (ISCAS, 2017)

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. - Marios Neofytou; Meiyi Zhou; Muhammed Bolatkale; Qilong Liu; Chenming Zhang; Georgi I. Radulov; Peter G. M. Baltus; Lucien J. Breems (ISCAS, 2018)

A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator. - Meiyi Zhou; Marios Neofytou; Muhammed Bolatkale; Qilong Liu; Chenming Zhang; Pierluigi Cenci; Georgi I. Radulov; Peter G. M. Baltus; Lucien J. Breems (ISCAS, 2018)

A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. - Pierluigi Cenci; Muhammed Bolatkale; Robert Rutten; M. Ganzerli; Gerard Lassche; Kofi A. A. Makinwa; Lucien J. Breems (VLSI Circuits, 2019)

Novel Baseband Analog Beamforming through Resistive DACs and Sigma Delta Modulators. - Stijn Ringeling; Loek Steinebach; Qilong Liu; Chenming Zhang; Shagun Bajoria; Muhammed Bolatkale; Lucien J. Breems; Georgi I. Radulov (ECCTD, 2020)

Analysis of the Inter-Stage Signal Leakage in Wide BW Low OSR and High DR CT MASH ΔΣM. - Qilong Liu; Lucien J. Breems; Shagun Bajoria; Muhammed Bolatkale; Chenming Zhang; Georgi I. Radulov (ISCAS, 2020)

A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS. - Chenming Zhang; Lucien J. Breems; Qilong Liu; Georgi I. Radulov; Muhammed Bolatkale; Shagun Bajoria; Robert Rutten; Arthur H. M. van Roermund (ESSCIRC, 2021)

A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW. - Pierluigi Cenci; Hans Brekelmans; Shagun Bajoria; Marcello Ganzerli; Bernard Burdiek; Robert Rutten; Yihan Gao; Muhammed Bolatkale; Paul Swinkels; Lucien J. Breems (ESSCIRC, 2022)

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC. - Shubham Mehrotra; Efraïm Eland; Shoubhik Karmakar; Angqi Liu; Burak Gönen; Muhammed Bolatkale; Robert H. M. van Veldhoven; Kofi A. A. Makinwa (ESSCIRC, 2022)

A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction. - Muhammed Bolatkale; Robert Rutten; Hans Brekelmans; Shagun Bajoria; Yihan Gao; Bernard Burdiek; Lucien J. Breems (ISSCC, 2022)

A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS. - Qilong Liu; Lucien J. Breems; Chenming Zhang; Shagun Bajoria; Muhammed Bolatkale; Robert Rutten; Georgi I. Radulov (ISSCC, 2022)

A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction. - Muhammed Bolatkale; Robert Rutten; Hans Brekelmans; Shagun Bajoria; Yihan Gao; Bernard Burdiek; Lucien J. Breems (IEEE J. Solid State Circuits, 2022)

A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS. - Qilong Liu; Lucien J. Breems; Shagun Bajoria; Muhammed Bolatkale; Robert Rutten; Georgi I. Radulov (IEEE J. Solid State Circuits, 2022)

A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW. - Sundeep Javvaji; Muhammed Bolatkale; Shagun Bajoria; Robert Rutten; Bert Oude-Essink; Koen Beijens; Kofi A. A. Makinwa; Lucien J. Breems (VLSI Technology and Circuits, 2023)

A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme. - Sundeep Javvaji; Muhammed Bolatkale; Shagun Bajoria; Robert Rutten; Bert Oude-Essink; Koen Beijens; Kofi A. A. Makinwa; Lucien J. Breems (IEEE J. Solid State Circuits, 2024)

A 6-GHz Continuous-Time Bandpass ΔΣ ADC With Background Filter Calibration and -100 dBc IM3 for a Mixer-Less DAB Band III Receiver. - Shagun Bajoria; Robert Rutten; Muhammed Bolatkale; Yihan Gao; Hans Brekelmans; Bernard Burdiek; Hendrik van der Ploeg; Lucien J. Breems (IEEE J. Solid State Circuits, 2025)