Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection. - Muhannad S. Bakir; Hollie A. Reed; Anthony V. Mulé; Paul A. Kohl; Kevin P. Martin; James D. Meindl (CICC, 2002)

Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution. - Kaveh Shakeri; Muhannad S. Bakir; James D. Meindl (SoCC, 2004)

Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities. - Azad Naeemi; Muhannad S. Bakir (SoCC, 2006)

Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems. - Muhannad S. Bakir; Bing Dang; James D. Meindl (CICC, 2007)

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. - Muhannad S. Bakir; Calvin King; Deepak C. Sekar; Hiren D. Thacker; Bing Dang; Gang Huang; Azad Naeemi; James D. Meindl (CICC, 2008)

Co-design of signal, power, and thermal distribution networks for 3D ICs. - Young-Joon Lee; Yoon Jo Kim; Gang Huang; Muhannad S. Bakir; Yogendra K. Joshi; Andrei G. Fedorov; Sung Kyu Lim (DATE, 2009)

Nanoelectronics in retrospect, prospect and principle. - James D. Meindl; Azad Naeemi; Muhannad S. Bakir; R. Murali (ISSCC, 2010)

Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer. - Li Zheng; Muhannad S. Bakir (SoCC, 2012)

Evaluation of 3DICs and fabrication of monolithic interlayer vias. - William Wahby; Ashish Dembla; Muhannad S. Bakir (3DIC, 2013)

Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICs. - Yue Zhang; Hanju Oh; Muhannad S. Bakir (3DIC, 2013)

Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation. - Yang Zhang; Thomas E. Sarvey; Muhannad S. Bakir (3DIC, 2014)

Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnects. - Chaoqi Zhang 001; Paragkumar Thadesar; Muneeb Zia; Thomas E. Sarvey; Muhannad S. Bakir (3DIC, 2014)

Silicon interposer platform with low-loss through-silicon vias using air. - Hanju Oh; Gary S. May; Muhannad S. Bakir (3DIC, 2015)

Fabrication of and cell growth on 'silicon membranes' with high density TSVs for bio-sensing applications. - Muneeb Zia; Chaoqi Zhang 001; Paragkumar Thadesar; Tracy Hookway; Taiyun Chi; Joe L. Gonzalez; Todd C. McDevitt; Hua Wang 006; Muhannad S. Bakir (BioCAS, 2015)

Embedded cooling technologies for densely integrated electronic systems. - Thomas E. Sarvey; Yang Zhang; Li Zheng; Paragkumar Thadesar; Ravi Gutala; Colman Cheung; Arifur Rahman; Muhannad S. Bakir (CICC, 2015)

The impact of 3D stacking on GPU-accelerated deep neural networks: An experimental study. - William Wahby; Thomas E. Sarvey; Hardik Sharma; Hadi Esmaeilzadeh; Muhannad S. Bakir (3DIC, 2016)

Design considerations for 2.5-D and 3-D integration accounting for thermal constraints. - Yang Zhang; Xuchen Zhang; William Wahby; Muhannad S. Bakir (3DIC, 2016)

Chip-to-chip interconnect integration technologies. - Muneeb Zia; Chaoqi Zhang 001; Hyun Suk Yang; Li Zheng; Muhannad S. Bakir (IEICE Electron. Express, 2016)

Microfabrication, assembly, and hermetic packaging of mm-sized free-floating neural probes. - Pyungwoo Yeon; Joe L. Gonzalez; Muneeb Zia; Sreejith Kochupurackal Rajan; Gary S. May; Muhannad S. Bakir; Maysam Ghovanloo (BioCAS, 2017)

PhD forum: Heterogeneous interconnection of ICs using stitch-chips. - Muhannad S. Bakir (VLSI-SoC, 2017)

Towards a 1.1 mm2 free-floating wireless implantable neural recording SoC. - Pyungwoo Yeon; Muhannad S. Bakir; Maysam Ghovanloo (CICC, 2018)

High Density and Low-Temperature Interconnection Enabled by Mechanical Self-Alignment and Electroless Plating. - Sreejith Kochupurackal Rajan; Ming Jui Li; Muhannad S. Bakir; Gary S. May (3DIC, 2019)

A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. - Rakshith Saligram; Ankit Kaul; Muhannad S. Bakir; Arijit Raychowdhury (VLSI-SOC, 2020)

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication. - Rakshith Saligram; Ankit Kaul; Muhannad S. Bakir; Arijit Raychowdhury (VLSI-SoC (Selected Papers), 2020)

Design Space Exploration of Power Delivery For Advanced Packaging Technologies. - Md Obaidul Hossen; Yang Zhang; Hesam Fathi Moghadam; Yue Zhang; Michael Dayringer; Muhannad S. Bakir (CoRR, 2020)

Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance. - Ankit Kaul; Yandong Luo; Xiaochen Peng; Shimeng Yu; Muhannad S. Bakir (3DIC, 2021)

Electrical and Performance Benefits of Advanced Monolithic Cooling for 2.5D Heterogeneous ICs. - Sreejith Kochupurackal Rajan; Ankit Kaul; Gary S. May; Muhannad S. Bakir (3DIC, 2021)

High-performance Flexible Microelectrode Array with PEDOT: PSS Coated 3D Micro-cones for Electromyographic Recording. - Jiaao Lu; Muneeb Zia; Matthew J. Williams; Amanda L. Jacob; Bryce Chung; Samuel J. Sober; Muhannad S. Bakir (EMBC, 2022)

Integrated Silicon Microfluidic Cooling of a High-Power Overclocked CPU for Efficient Thermal Management. - Sreejith Kochupurackal Rajan; Bharath Ramakrishnan; Husam Alissa; Washington Kim; Christian Belady; Muhannad S. Bakir (IEEE Access, 2022)

A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect. - Yandong Luo; Sourav Dutta; Ankit Kaul; Sung Kyu Lim; Muhannad S. Bakir; Suman Datta; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention. - Wantong Li; Madison Manley; James Read; Ankit Kaul; Muhannad S. Bakir; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators. - Ankit Kaul; Madison Manley; James Read; Yandong Luo; Xiaochen Peng; Shimeng Yu; Muhannad S. Bakir (VLSI Technology and Circuits, 2024)

A 32-Channel 85.4dB SNDR Time-multiplexed Neural Recording Frontend Achieving Within-Conversion Artifact Recovery. - Arindam Mandal; Chi-Hsiang Huang 001; Julian Arenas; Wei-En Lee; Philip Anschutz; Amanda L. Jacob; Keshav Ramachandra; Samuel J. Sober; Muhannad S. Bakir; Shaolan Li; Visvesh S. Sathe 001 (CICC, 2025)

Exploiting Chiplet Integration Technology for Fast High-Capacity DRAM Modules. - Zihan Xia; Chihun Song; Ram Krishna; Ashita Victor; Srujan Penta; Muhannad S. Bakir; Elyse Rosenbaum; Nam Sung Kim; Mingu Kang (IEEE Trans. Very Large Scale Integr. Syst., 2025)