A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure. - Sanjive Agarwala; Arjun Rajagopal; Anthony M. Hill; Mayur Joshi; Steven Mullinnix; Timothy Anderson; Raguram Damodaran; Lewis Nardini; Paul Wiley; Peter Groves; John Apostol; Michael Gill; et al. (ISSCC, 2007)

A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS. - Timothy Anderson; Duc Bui; Shriram Moharil; Soujanya Narnur; Mujibur Rahman; Anthony Lell; Eric Biscondi; Ashish Shrivastava; Peter Dent; Mingjian Yan; Hasan Mahmood (IEEE Symposium on Computer Arithmetic, 2011)

A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS. - Raguram Damodaran; Timothy Anderson; Sanjive Agarwala; Rama Venkatasubramanian; Michael Gill; Dhileep Gopalakrishnan; Anthony M. Hill; Abhijeet Chachad; Dheera Balasubramanian; Naveen Bhoria; Jonathan Tran; Duc Bui; et al. (VLSI Design, 2012)

Heterogeneous Multi-processor Coherent Interconnect. - Kai Chirca; Matthew Pierson; Joe Zbiciak; David Thompson; Daniel Wu; Shankar Myilswamy; Roger Griesmer; Kedar Basavaraj; Thomas Huynh; Akshit Dayal; Junbok You; Patrick Eyres; et al. (Hot Interconnects, 2013)

Geometric Interpretation of the Multi-solution Phenomenon in the P3P Problem. - Bo Wang; Hao Hu; Mujibur Rahman; Caixia Zhang (J. Math. Imaging Vis., 2020)