A dynamic programming solution for optimizing test delivery in multicore SOCs. - Mukesh Agrawal 001; Michael Richter 002; Krishnendu Chakrabarty (ITC, 2012)

A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs. - Mukesh Agrawal 001; Krishnendu Chakrabarty (ITC, 2013)

Test-cost optimization and test-flow selection for 3D-stacked ICs. - Mukesh Agrawal 001; Krishnendu Chakrabarty (VTS, 2013)

A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs. - Mukesh Agrawal 001; Krishnendu Chakrabarty; Bill Eklow (ITC, 2014)

Test-time optimization in NOC-based manycore SOCs using multicast routing. - Mukesh Agrawal 001; Krishnendu Chakrabarty (VTS, 2014)

Test and Design-for-Testability Solutions for 3D Integrated Circuits. - Krishnendu Chakrabarty; Mukesh Agrawal 001; Sergej Deutsch; Brandon Noia; Ran Wang 002; Fangming Ye (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Test-Delivery Optimization in Manycore SOCs. - Mukesh Agrawal 001; Michael Richter 002; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs. - Mukesh Agrawal 001 (2014)

Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs. - Mukesh Agrawal 001; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Reuse-Based Optimization for Prebond and Post-Bond Testing of 3-D-Stacked ICs. - Mukesh Agrawal 001; Krishnendu Chakrabarty; Randy Widialaksono (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

The hype, myths, and realities of testing 3D integrated circuits. - Ran Wang 002; Sergej Deutsch; Mukesh Agrawal 001; Krishnendu Chakrabarty (ICCAD, 2016)

A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs. - Mukesh Agrawal 001; Krishnendu Chakrabarty; Bill Eklow (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches. - Mainak Chaudhuri; Mukesh Agrawal 001; Jayesh Gaur; Sreenivas Subramoney (ACM Trans. Archit. Code Optim., 2017)