Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS. - Mukesh Kumar Srivastav; Rimjhim; Govind Soni; Umang Mittal; Rupali Tewari; Riya Yadav; Anuj Grover; Kedar Janardan Dhori; Harsh Rawat (ICECS, 2021)

3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS. - Mukesh Kumar Srivastav; Rimjhim; Roshan Mishra; Anuj Grover; Kedar Janardan Dhori; Harsh Rawat (ISCAS, 2022)