Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. - Mukesh Ranjan; Wim Verhaegen; Anuradha Agarwal; Hemanth Sampath; Ranga Vemuri; Georges G. E. Gielen (DATE, 2004)

Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. - Huiying Yang; Mukesh Ranjan; Wim Verhaegen; Mengmeng Ding; Ranga Vemuri; Georges G. E. Gielen (ASP-DAC, 2005)

Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. - Mukesh Ranjan; Ranga Vemuri (ISCAS, 2006)

Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. - Ritochit Chakraborty; Mukesh Ranjan; Ranga Vemuri (VLSI Design, 2006)