Towards Incorporating Device Parameter Variations in Timing Analysis. - Mukund Sivaraman; Andrzej J. Strojwas (EDAC-ETC-EUROASIC, 1994)

Test Vector Generation for Parametric Path Delay Faults. - Mukund Sivaraman; Andrzej J. Strojwas (ITC, 1995)

Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. - Mukund Sivaraman; Andrzej J. Strojwas (ICCAD, 1996)

Diagnosis of parametric path delay faults. - Mukund Sivaraman; Andrzej J. Strojwas (VLSI Design, 1996)

A diagnosability metric for parametric path delay faults. - Mukund Sivaraman; Andrzej J. Strojwas (VTS, 1996)

Timing analysis based on primitive path delay fault identification. - Mukund Sivaraman; Andrzej J. Strojwas (ICCAD, 1997)

Primitive Path Delay Fault Identification. - Mukund Sivaraman; Andrzej J. Strojwas (VLSI Design, 1997)

Primitive path delay faults: identification and their use in timinganalysis. - Mukund Sivaraman; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Path delay fault diagnosis and coverage-a metric and an estimationtechnique. - Mukund Sivaraman; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Cycle-time aware architecture synthesis of custom hardware accelerators. - Mukund Sivaraman; Shail Aditya (CASES, 2002)

PICO: Automatically Designing Custom Computers. - Vinod Kathail; Shail Aditya; Robert Schreiber; B. Ramakrishna Rau; Darren C. Cronquist; Mukund Sivaraman (Computer, 2002)

PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. - Robert Schreiber; Shail Aditya; Scott A. Mahlke; Vinod Kathail; B. Ramakrishna Rau; Darren C. Cronquist; Mukund Sivaraman (J. VLSI Signal Process., 2002)