On properties of Kleene TDDs. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ASP-DAC, 1997)

On Decomposition of Kleene TDDs. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (Asian Test Symposium, 1997)

Realization of Regular Ternary Logic Functions. - Yukihiro Iguchi; Munehiro Matsuura; Tsutomu Sasao; Atsumu Iseno (ASP-DAC, 1999)

A hardware simulation engine based on decision diagrams (short paper). - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura; Atsumu Iseno (ASP-DAC, 2000)

Implementation of Multiple-Output Functions Using PQMDDs. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2000)

Realization of Multiple-Output Functions by Reconfigurable Cascades. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ICCD, 2001)

Representations of Logic Functions Using QRMDDs. - Shinobu Nagayama; Tsutomu Sasao; Yukihiro Iguchi; Munehiro Matsuura (ISMVL, 2002)

Comparison of Decision Diagrams for Multiple-Output Logic Functions. - Tsutomu Sasao; Yukihiro Iguchi; Munehiro Matsuura (IWLS, 2002)

Bi-Partition of Shared Binary Decision Diagrams. - Munehiro Matsuura; Tsutomu Sasao; Jon T. Butler; Yukihiro Iguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Evaluation of multiple-output logic functions using decision diagrams. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ASP-DAC, 2003)

A method to decompose multiple-output logic functions. - Tsutomu Sasao; Munehiro Matsuura (DAC, 2004)

A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2004)

BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. - Tsutomu Sasao; Munehiro Matsuura (DAC, 2005)

A Design Algorithm for Sequential Circuits Using LUT Rings. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Average Path Length of Binary Decision Diagrams. - Jon T. Butler; Tsutomu Sasao; Munehiro Matsuura (IEEE Trans. Computers, 2005)

A fast logic simulator using a look up table cascade emulator. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ASP-DAC, 2006)

On Designs of Radix Converters Using Arithmetic Decompositions. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2006)

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

An Implementation of an Address Generator Using Hash Memories. - Tsutomu Sasao; Munehiro Matsuura (DSD, 2007)

A CAM Emulator Using Look-Up Table Cascades. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IPDPS, 2007)

On Designs of Radix Converters Using Arithmetic Decompositions–Binary to Decimal Converters–. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2007)

Design Methods of Radix Converters Using Arithmetic Decompositions. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2007)

BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades. - Munehiro Matsuura; Tsutomu Sasao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (J. Multiple Valued Log. Soft Comput., 2007)

A Parallel Branching Program Machine for Emulation of Sequential Circuits. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (ARC, 2009)

The Parallel Sieve Method for a Virus Scanning Engine. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (DSD, 2009)

Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. - Tsutomu Sasao; Takaaki Nakamura; Munehiro Matsuura (DSD, 2009)

A virus scanning engine using a parallel finite-input memory machine and MPUs. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (FPL, 2009)

A Quaternary Decision Diagram Machine and the Optimization of its Code. - Tsutomu Sasao; Hiroki Nakahara; Munehiro Matsuura; Yoshifumi Kawamura; Jon T. Butler (ISMVL, 2009)

A Packet Classifier Using a Parallel Branching Program Machine. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (DSD, 2010)

A Comparison of Architectures for Various Decision Diagram Machines. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2010)

A regular expression matching using non-deterministic finite automaton. - Hiroshi Nakahara; Tsutomu Sasao; Munehiro Matsuura (MEMOCODE, 2010)

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (IEICE Trans. Inf. Syst., 2010)

A Quaternary Decision Diagram Machine: Optimization of Its Code. - Tsutomu Sasao; Hiroki Nakahara; Munehiro Matsuura; Yoshifumi Kawamura; Jon T. Butler (IEICE Trans. Inf. Syst., 2010)

A Regular Expression Matching Circuit Based on a Decomposed Automaton. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ARC, 2011)

A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2011)

A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ARC, 2012)

Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2012)

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2012)

A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (Microprocess. Microsystems, 2012)

A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (J. Multiple Valued Log. Soft Comput., 2012)

An Architecture for IPv6 Lookup Using Parallel Index Generation Units. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ARC, 2013)

A packet classifier using LUT cascades based on EVMDDS (k). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (FPL, 2013)

A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2013)

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2013)

An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2014)

A Packet Classifier Based on Prefetching EVMDD (k) Machines. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2014)

A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (J. Multiple Valued Log. Soft Comput., 2014)

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Hisashi Iwamoto; Yasuhiro Terao (IEICE Trans. Inf. Syst., 2015)

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. - Hiroki Nakahara; Tsutomu Sasao; Hisashi Iwamoto; Munehiro Matsuura (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Hisashi Iwamoto (J. Multiple Valued Log. Soft Comput., 2016)