An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF). - Tadashi Maeda; Keiichi Numata; Masahiro Fujii; Masatoshi Tokushima; Shigeki Wada; Muneo Fukaishi; Masaoki Ishikawa (IEEE J. Solid State Circuits, 1996)

A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's. - Tadashi Maeda; Keiichi Numata; Masatoshi Tokushima; Masaoki Ishikawa; Muneo Fukaishi; Hikam Hida; Yasuo Ohno (IEEE J. Solid State Circuits, 1996)

A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture. - Muneo Fukaishi; Kazuyuki Nakamura; Masaharu Sato; Yutaka Tsutsui; Syuji Kishi; Michio Yotsuyanagi (IEEE J. Solid State Circuits, 1998)

A 150 mW 8: 1 MUX and a 170 mW 1: 8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's. - Masahiro Fujii; Keiichi Numata; Tadashi Maeda; Masatoshi Tokushima; Shigeki Wada; Muneo Fukaishi; Masaoki Ishikawa (IEEE Trans. Very Large Scale Integr. Syst., 1998)

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications. - Muneo Fukaishi; Satoshi Nakamura; Akio Tajima; Yasushi Kinoshita; Yoshihiko Suemura; Hisamitsu Suzuki; Toshiro Itani; Hidenobu Miyamoto; Naoya Henmi; Tohru Yamazaki; Michio Yotsuyanagi (IEEE J. Solid State Circuits, 1999)

A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays. - Muneo Fukaishi; Kazuyuki Nakamura; Hideki Heiuchi; Yoshinori Hirota; Yoetsu Nakazawa; Hidenori Ikeno; Hiroshi Hayama; Michio Yotsuyanagi (IEEE J. Solid State Circuits, 2000)

A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. - Koichiro Minami; Muneo Fukaishi; Masayuki Mizuno; Hideaki Onishi; Kenji Noda; Kiyotaka Imai; Tadahiko Horiuchi; Hiroshi Yamaguchi; Takanori Sato; Kazuyuki Nakamura; Masakazu Yaniashina (CICC, 2001)

Optical interconnection as an IP macro of a CMOS library. - Takashi Yoshikawa; Ichiro Hatakeyama; Kazunori Miyoshi; Kazuhiko Kurata; Juni-Ichi Sasaki; Nobuharu Kami; Takara Sugimoto; Muneo Fukaishi; Kazuyuki Nakamura; Kei Tanaka; Hiroaki Nishi; Tomohiro Kudoh (Hot Interconnects, 2001)

A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture. - Kouichi Yamaguchi; Muneo Fukaishi; Takehiko Sakamoto; Naoto Akiyama; Kazuyuki Nakamura (IEEE J. Solid State Circuits, 2001)

A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer. - Yoshiharu Kudoh; Muneo Fukaishi; Masayuki Mizuno (IEEE J. Solid State Circuits, 2003)

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2006)

Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. - Keishi Ohashi; Junichi Fujikata; Masafumi Nakada; Tsutomu Ishi; Kenichi Nishi; Hirohito Yamada; Muneo Fukaishi; Masayuki Mizuno; Koichi Nose; Ichiro Ogura; Yutaka Urino; Toshio Baba (ISSCC, 2006)

Channel-Count-Independent BIST for Multi-Channel SerDes. - Kouichi Yamaguchi; Muneo Fukaishi (IEICE Trans. Electron., 2006)

Multi-GB/s Transceivers. - Robert Payne; Muneo Fukaishi (ISSCC, 2007)

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI. - Alexandre Siligaris; Yasuhiro Hamada; Christopher Mounet; Christine Raynaud; Baudouin Martineau; Nicolas Deparis; Nathalie Rolland; Muneo Fukaishi; Pierre Vincent (ESSCIRC, 2009)

A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. - Takashi Tokairin; Mitsuji Okada; Masaki Kitsunezuka; Tadashi Maeda; Muneo Fukaishi (ISSCC, 2010)

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI. - Alexandre Siligaris; Yasuhiro Hamada; Christopher Mounet; Christine Raynaud; Baudouin Martineau; Nicolas Deparis; Nathalie Rolland; Muneo Fukaishi; Pierre Vincent (IEEE J. Solid State Circuits, 2010)

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. - Takashi Tokairin; Mitsuji Okada; Masaki Kitsunezuka; Tadashi Maeda; Muneo Fukaishi (IEEE J. Solid State Circuits, 2010)

Real-time current-waveform sensor with plugless energy harvesting from AC power lines for home/building energy-management systems. - Shingo Takahashi; Nobuhide Yoshida; Kenichi Maruhashi; Muneo Fukaishi (ISSCC, 2011)

A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme. - Masaki Kitsunezuka; Takashi Tokairin; Tadashi Maeda; Muneo Fukaishi (IEEE J. Solid State Circuits, 2011)

A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems. - Masaki Kitsunezuka; Hiroshi Kodama; Naoki Oshima; Kazuaki Kunihiro; Tadashi Maeda; Muneo Fukaishi (IEEE J. Solid State Circuits, 2012)