Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process. - Munish Malik; Ajay Kumar; H. S. Jatana (VDAT, 2017)

Comparative analysis of radiation tolerant analog circuit layout in 180 nm CMOS technology for space application. - Munish Malik; Neelam Rup Prakash; Ajay Kumar (Microelectron. J., 2023)

Analyzing the Effectiveness of Various NMOS Layouts for Total Ionizing Dose Hardening in 180nm CMOS. - Munish Malik; Neelam Rup Prakash; Ajay Kumar; Jasbir Kaur; Amit Singh; Kavita Monga (J. Electron. Test., 2025)