Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. - Nirav Dave; Kermin Fleming; Myron King; Michael Pellauer; Muralidaran Vijayaraghavan (MEMOCODE, 2007)

From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols. - Man Cheuk Ng; Muralidaran Vijayaraghavan; Nirav Dave; Arvind 001; Gopal Raghavan; Jamey Hicks (MEMOCODE, 2007)

A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. - Michael Pellauer; Muralidaran Vijayaraghavan; Michael Adler; Arvind 001; Joel S. Emer (FPGA, 2008)

Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. - Michael Pellauer; Muralidaran Vijayaraghavan; Michael Adler; Arvind 001; Joel S. Emer (ISPASS, 2008)

High-throughput Pipelined Mergesort. - Kermin Fleming; Myron King; Man Cheuk Ng; Asif Khan 005; Muralidaran Vijayaraghavan (MEMOCODE, 2008)

Implementing a fast cartesian-polar matrix interpolator. - Abhinav Agarwal; Nirav Dave; Kermin Fleming; Asif Khan 005; Myron King; Man Cheuk Ng; Muralidaran Vijayaraghavan (MEMOCODE, 2009)

Bounded Dataflow Networks and Latency-Insensitive circuits. - Muralidaran Vijayaraghavan; Arvind 001 (MEMOCODE, 2009)

A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. - Michael Pellauer; Muralidaran Vijayaraghavan; Michael Adler; Arvind 001; Joel S. Emer (ACM Trans. Reconfigurable Technol. Syst., 2009)

Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). - Michael Pellauer; Abhinav Agarwal; Asif Khan 005; Man Cheuk Ng; Muralidaran Vijayaraghavan; Forrest Brewer; Joel S. Emer (MEMOCODE, 2010)

Fast and cycle-accurate modeling of a multicore processor. - Asif Khan 005; Muralidaran Vijayaraghavan; Silas Boyd-Wickizer; Arvind 001 (ISPASS, 2012)

A general technique for deterministic model-cycle-level debugging. - Asif Khan 005; Muralidaran Vijayaraghavan; Arvind 001 (MEMOCODE, 2012)

Modular compilation of guarded atomic actions. - Muralidaran Vijayaraghavan; Nirav Dave; Arvind 001 (MEMOCODE, 2013)

A new synthesis procedure for atomic rules containing multi-cycle function blocks. - Michal Karczmarek; Arvind 001; Muralidaran Vijayaraghavan (MEMOCODE, 2014)

Modular Deductive Verification of Multiprocessor Hardware Designs. - Muralidaran Vijayaraghavan; Adam Chlipala; Arvind 001; Nirav Dave (CAV (2), 2015)

A Proof of Correctness for the Tardis Cache Coherence Protocol. - Xiangyao Yu; Muralidaran Vijayaraghavan; Srinivas Devadas (CoRR, 2015)

Taming Weak Memory Models. - Sizhuo Zhang; Arvind 001; Muralidaran Vijayaraghavan (CoRR, 2016)

Modular verification of hardware systems. - Muralidaran Vijayaraghavan (2016)

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility. - Sizhuo Zhang; Muralidaran Vijayaraghavan; Arvind 001 (PACT, 2017)

An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution. - Sizhuo Zhang; Muralidaran Vijayaraghavan; Arvind 001 (CoRR, 2017)

Weak Memory Models with Matching Axiomatic and Operational Definitions. - Sizhuo Zhang; Muralidaran Vijayaraghavan; Dan Lustig; Arvind 001 (CoRR, 2017)

Kami: a platform for high-level parametric hardware specification and its modular verification. - Joonwon Choi; Muralidaran Vijayaraghavan; Benjamin Sherman; Adam Chlipala; Arvind 001 (Proc. ACM Program. Lang., 2017)

Constructing a Weak Memory Model. - Sizhuo Zhang; Muralidaran Vijayaraghavan; Andrew Wright; Mehdi Alipour; Arvind 001 (ISCA, 2018)