ReOPUF: Relaxation Oscillator Physical Unclonable Function for Reliable Key Generation in IoT Security. - Raveendra Podeti; Srihari Rao Patri; Srinivas Katkoori; Muralidhar Pullakandam (IFIPIoT, 2021)

Highly reliable XoR Feed Arbiter Physical Unclonable Function (XFAPUF) in 180 nm process for IoT security. - Raveendra Podeti; Sreehari Rao Patri; Muralidhar Pullakandam (Microprocess. Microsystems, 2021)

Efficient successive cancellation decoder architecture for multi-kernel polar codes. - Nandini Jali; Muralidhar Pullakandam; Sreehari Rao Patri (iSES, 2022)

The chaotic-based challenge feed mechanism for Arbiter Physical Unclonable Functions (APUFs) with enhanced reliability in IoT security. - Raveendra Podeti; Sreehari Rao Patri; Muralidhar Pullakandam (iSES, 2022)

An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (iSES, 2022)

Advanced Powerplanning Strategy Utilising Aprisa - Image Edge Detector. - Roshan Agarwal; Muralidhar Pullakandam; Gopinath Agrahara; Amarnadh Akavarapu (ICCCNT, 2023)

Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU. - Sujay Kumar Mandal; Muralidhar Pullakandam; Rama Muni Reddy Yanamala (ICCCNT, 2023)

SoC-based real-time SVM classification with integrated training using HLS and PYNQ. - B. B. Shabarinath; Muralidhar Pullakandam (Microprocess. Microsystems, 2023)

A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (Des. Autom. Embed. Syst., 2023)

Empowering edge devices: FPGA-based 16-bit fixed-point accelerator with SVD for CNN on 32-bit memory-limited systems. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (Int. J. Circuit Theory Appl., 2024)

High-Speed Power Allocation in NOMA System Using FPGA-Based DNN. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (J. Circuits Syst. Comput., 2024)

Embedded Hardware-Efficient FPGA Architecture for SVM Learning and Inference. - B. B. Shabarinath; Muralidhar Pullakandam (IEEE Access, 2025)

FPGA-accelerated hybrid CNN-LSTM system for efficient EEG-based drowsiness recognition. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (J. Supercomput., 2025)