A New Statistical Optimization Algorithm for Gate Sizing. - Murari Mani; Michael Orshansky (ICCD, 2004)

An efficient algorithm for statistical minimization of total power under timing yield constraints. - Murari Mani; Anirudh Devgan; Michael Orshansky (DAC, 2005)

Statistical technology mapping for parametric yield. - Ashish Kumar Singh; Murari Mani; Michael Orshansky (ICCAD, 2005)

Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. - Ashish Kumar Singh; Murari Mani; Ruchir Puri; Michael Orshansky (DAC, 2006)

Application of fast SOCP based statistical sizing in the microprocessor design flow. - Murari Mani; Mahesh Sharma; Michael Orshansky (ACM Great Lakes Symposium on VLSI, 2006)

Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. - Murari Mani; Ashish Kumar Singh; Michael Orshansky (ICCAD, 2006)

A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. - Murari Mani; Anirudh Devgan; Michael Orshansky; Yaping Zhan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Large-scale multi-corner leakage optimization under the sign-off timing environment. - George Gonzalez; Murari Mani; Mahesh Sharma (ISQED, 2015)