A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS. - Prema Kumar Govindaswamy; Mursina Khatun; Vijay Shankar Pasupureddi (ISCAS, 2024)

A 27-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS. - Prema Kumar Govindaswamy; Mursina Khatun; Vijay Shankar Pasupureddi (ISCAS, 2024)

A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS. - Prema Kumar Govindaswamy; Mursina Khatun; Vijay Shankar Pasupureddi (ISQED, 2024)