Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. - Ji Chel Bea; Mariappan Murugesan; Yuki Ohara; Akihiro Noriki; Hisashi Kino; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. - Yuki Ohara; Akihiro Noriki; Katsuyuki Sakuma; Kang Wook Lee 002; Mariappan Murugesan; Jichoel Bea; Fumiaki Yamada; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. - Takafumi Fukushima; Eiji Iwata; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. - Mariappan Murugesan; Yuki Ohara; Jichoel Bea; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

Temporary bonding strength control for self-assembly-based 3D integration. - Takafumi Fukushima; Yuki Ohara; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress. - Mariappan Murugesan; Hideto Hashiguchi; Harufumi Kobayashi; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

High density Cu-TSVs and reliability issues. - Mariappan Murugesan; Harufumi Kobayashi; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration. - Takafumi Fukushima; Takayuki Konno; Eiji Iwata; Risato Kobayashi; Toshiya Kojima; Mariappan Murugesan; Ji Chel Bea; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (Micromachines, 2011)

Development of via-last 3D integration technologies using a new temporary adhesive system. - Takafumi Fukushima; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Mitsumasa Koyanagi (3DIC, 2013)

3D memory chip stacking by multi-layer self-assembly technology. - Takafumi Fukushima; Jichoel Bea; Mariappan Murugesan; Ho-Young Son; Min-Suk Suh; K.-Y. Byun; N.-S. Kim; Kang Wook Lee 002; Mitsumasa Koyanagi (3DIC, 2013)

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. - Kang Wook Lee 002; Seiya Tanikawa; Mariappan Murugesan; H. Naganuma; Jichoel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2013)

Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV. - Mariappan Murugesan; Jichoel Bea; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi; Yuji Sutou; H. Wang; J. Koike (3DIC, 2013)

Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration. - Takafumi Fukushima; Yuka Ito; Mariappan Murugesan; Jicheol Bea; Kang Wook Lee 002; Koji Choki; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2014)

Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV. - K. W. Lee; Chisato Nagai; Ai Nakamura; Ji Chel Bea; Mariappan Murugesan; Takafumi Fukushima; Tanaka Tanaka; Mitsumasa Koyanagi (3DIC, 2014)

Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI. - Mariappan Murugesan; Takafumi Fukushima; Ji Chel Bea; K. W. Lee; Mitsu Koyanagi; Y. Imai; S. Kimura; Tetsu Tanaka (3DIC, 2014)

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. - Takafumi Fukushima; Taku Suzuki; Hideto Hashiguchi; Chisato Nagai; Jichoel Bea; Hiroyuki Hashimoto; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Kazushi Asami; Yasuhiro Kitamura; Mitsumasa Koyanagi (3DIC, 2015)

Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study. - Mariappan Murugesan; Jichoel Bea; Hiroyuki Hashimoto; K. W. Lee; Mitsu Koyanagi; Takafumi Fukushima; Tetsu Tanaka (3DIC, 2015)

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. - Kang Wook Lee 002; Ji Chel Bea; Mariappan Murugesan; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (IRPS, 2015)

New concept of TSV formation methodology using Directed Self-Assembly (DSA). - Takafumi Fukushima; Mariappan Murugesan; Shin Ohsaki; Hiroyuki Hashimoto; Jichoel Bea; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2016)

3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions. - Makoto Motoyoshi; Kohki Yanagimura; Taikoh Fushimi; Junichi Takanohashi; Mariappan Murugesan; Masahiro Aoyagi; Mitsumasa Koyanagi (3DIC, 2016)

Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology. - Mariappan Murugesan; Jichel Bea; Takafumi Fukushima; Makoto Motoyoshi; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2016)

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration. - Takafumi Fukushima; Hideto Hashiguchi; Hiroshi Yonekura; Hisashi Kino; Mariappan Murugesan; Ji Chel Bea; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (Micromachines, 2016)

Intra- and inter-chip electrical interconnection formed by directed self assembly of nanocomposite containing diblock copolymer and nanometal. - Mariappan Murugesan; Takafumi Fukushima; Ji Chel Bea; Hiroyuki Hashimoto; Mitsu Koyanagi (IRPS, 2018)

Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation. - Rui Liang; Sungho Lee; Yuki Miwa; Kousei Kumahara; Mariappan Murugesan; Hisashi Kino; Takafumi Fukushima; Tetsu Tanaka (3DIC, 2019)

Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI. - Mariappan Murugesan; Mitsumasa Koyanagi; Takafumi Fukushima (3DIC, 2019)

Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration. - Mariappan Murugesan; Mitsumasa Koyanagi; Hiroyuki Hashimoto; Ji Chel Bea; Takafumi Fukushima (3DIC, 2019)

Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing. - Takafumi Fukushima; Shinichi Sakuyama; Masatomo Takahashi; Hiroyuki Hashimoto; Jichoel Bea; Theodorus Marcello; Hisashi Kino; Tetsu Tanaka; Mitsumasa Koyanagi; Mariappan Murugesan (3DIC, 2021)

Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications. - Mariappan Murugesan; E. Sone; A. Simomura; Makoto Motoyoshi; Masahiro Sawa; K. Fukuda; Mitsumasa Koyanagi; Takafumi Fukushima (3DIC, 2021)

Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding. - Mariappan Murugesan; Masahiro Sawa; E. Sone; Makoto Motoyoshi; Mitsumasa Koyanagi; Takafumi Fukushima (3DIC, 2023)

Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last. - Jiayi Shen; Chang Liu; Tadaaki Hoshi; Atsushi Shinoda; Hisashi Kino; Tetsu Tanaka; Mariappan Murugesan; Mitsumasa Koyanagi; Takafumi Fukushima (3DIC, 2023)

Antioxidative Cu Electrodeposition for 3D Interconnects with Hybrid Bonding. - Ryo Aizawa; Masahiro Sawa; Jinta Nampo; Yurina Fukumoto; Murugesan Mariappan; Takafumi Fukushima (3DIC, 2024)

Impact of Cu Pad Density on Cu-CMP and Bonding Yield for Chip-to-Wafer Hybrid Bonding. - Mariappan Murugesan; Hiroyuki Hashimoto; Kentaro Mihara; Takashi Hare; Takafumi Fukushima; Fumihiro Inoue; Akira Uedono (3DIC, 2024)

Characterization of Ozone-Ethylene Radical Pretreatment for Hybrid Bonding without Water Rinsing Processes. - Bungo Tanaka; Tatsunori Shino; Murugesan Mariappan; Tetsu Tanaka; Takafumi Fukushima (3DIC, 2024)