BANDIT: embedding analog-to-digital converters on digital telecom ASICs. - Stéphane Donnay; Marc van Heijningen; Mustafa Badaroglu; Wim Diels; Marc Engels; Ivo Bolsens; Yann A. Zinzius; Georges G. E. Gielen; Willy Sansen; Tony Fondén; Svante Signell (ICECS, 1999)

High-level simulation of substrate noise generation including power supply noise coupling. - Marc van Heijningen; Mustafa Badaroglu; Stéphane Donnay; Marc Engels; Ivo Bolsens (DAC, 2000)

High-level simulation of substrate noise generation from large digital circuits with multiple supplies. - Mustafa Badaroglu; Marc van Heijningen; Vincent Gravot; Stéphane Donnay; Hugo De Man; Georges G. E. Gielen; Marc Engels; Ivo Bolsens (DATE, 2001)

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. - Mustafa Badaroglu; Kris Tiri; Stéphane Donnay; Piet Wambacq; Hugo De Man; Ingrid Verbauwhede; Georges G. E. Gielen (DAC, 2002)

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. - Mustafa Badaroglu; Marc van Heijningen; Vincent Gravot; John Compiet; Stéphane Donnay; Georges G. E. Gielen; Hugo J. De Man (IEEE J. Solid State Circuits, 2002)

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. - Marc van Heijningen; Mustafa Badaroglu; Stéphane Donnay; Georges G. E. Gielen; Hugo J. De Man (IEEE J. Solid State Circuits, 2002)

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. - Mustafa Badaroglu; Lakshmanan Balasubramanian; Kris Tiri; Vincent Gravot; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (ESSCIRC, 2003)

Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies. - Mustafa Badaroglu; Stéphane Donnay; Hugo J. De Man; Yann A. Zinzius; Georges G. E. Gielen; Willy Sansen; Tony Fondén; Svante Signell (IEEE J. Solid State Circuits, 2003)

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (CICC, 2004)

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. - Geert Van der Plas; Mustafa Badaroglu; Gerd Vandersteen; Petr Dobrovolný; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (DAC, 2004)

Digital Ground Bounce Reduction by Phase Modulation of the Clock. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (DATE, 2004)

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Lakshmanan Balasubramanian; Kris Tiri; Ingrid Verbauwhede; Stéphane Donnay; Georges G. E. Gielen; Hugo J. De Man (IEEE J. Solid State Circuits, 2004)

Digital ground bounce reduction by supply current shaping and clock frequency Modulation. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. - Julien Ryckaert; Claude Desset; Andrew Fort; Mustafa Badaroglu; Vincent De Heyn; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Bart van Poucke; Bert Gyselinckx (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. - Julien Ryckaert; Mustafa Badaroglu; Vincent De Heyn; Geert Van der Plas; Pierluigi Nuzzo 001; Andrea Baschirotto; Stefano D'Amico; Claude Desset; Hans Suys; Michael Libois; Bart van Poucke; Piet Wambacq; et al. (ISSCC, 2006)

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. - Mustafa Badaroglu; Claude Desset; Julien Ryckaert; Vincent De Heyn; Geert Van der Plas; Piet Wambacq; Bart van Poucke (EURASIP J. Wirel. Commun. Netw., 2006)

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. - Charlotte Soens; Geert Van der Plas; Mustafa Badaroglu; Piet Wambacq; Stéphane Donnay; Yves Rolain; Maarten Kuijk (IEEE J. Solid State Circuits, 2006)

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. - Mustafa Badaroglu; Kris Tiri; Geert Van der Plas; Piet Wambacq; Ingrid Verbauwhede; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Evolution of substrate noise generation mechanisms with CMOS technology scaling. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo J. De Man (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

SWAN: high-level simulation methodology for digital substrate noise generation. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Scalable Gate-Level Models for Power and Timing Analysis. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (ISCAS, 2007)

Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. - Claude Desset; Mustafa Badaroglu; Julien Ryckaert; Bart van Poucke (VTC Spring, 2007)

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. - Julien Ryckaert; Marian Verhelst; Mustafa Badaroglu; Stefano D'Amico; Vincent De Heyn; Claude Desset; Pierluigi Nuzzo 001; Bart van Poucke; Piet Wambacq; Andrea Baschirotto; Wim Dehaene; Geert Van der Plas (IEEE J. Solid State Circuits, 2007)

Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment. - Mustafa Badaroglu; Guy Decabooter; Francois Laulanet; Olivier Charlier (DATE, 2008)

A Cascadable Random Neural Network Chip with Reconfigurable Topology. - Mustafa Badaroglu; Ugur Halici; Isik Aybay; Cuneyt Cerkez (Comput. J., 2010)

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. - Arindam Mallik; Paul Zuber; Tsung-Te Liu; Bharani Chava; Bhavana Ballal; Pablo Royer Del Bario; Rogier Baert; Kris Croes; Julien Ryckaert; Mustafa Badaroglu; Abdelkarim Mercha; Diederik Verkest (DAC, 2013)

More Moore landscape for system readiness - ITRS2.0 requirements. - Mustafa Badaroglu; Kwok Ng; Mehdi Salmani Jelodar; SungGeun Kim; Gerhard Klimeck; Chorng-Ping Chang; Charles Cheung; Yuzo Fukuzaki (ICCD, 2014)

Holistic technology optimization and key enablers for 7nm mobile SoC. - Seung Chul Song; J. Xu; N. N. Mojumder; K. Rim; D. Yang; Jerry Bao; J. Zhu; Joseph Wang; Mustafa Badaroglu; V. Machkaoutsan; Praneeth Narayanasetti; B. Bucki; et al. (VLSIC, 2015)

Interconnect-aware device targeting from PPA perspective. - Mustafa Badaroglu; Jeff Xu (ICCAD, 2016)

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. - Seung Chul Song; J. Xu; D. Yang; K. Rim; P. Feng; Jerry Bao; J. Zhu; Joseph Wang; G. Nallapati; Mustafa Badaroglu; Praneeth Narayanasetti; B. Bucki; et al. (VLSI Circuits, 2016)

PPAC scaling enablement for 5nm mobile SoC technology. - Mustafa Badaroglu; Jeff Xu; John Zhu; Da Yang 007; Jerry Bao; Seung Chul Song; Peijie Feng; Romain Ritzenthaler; Hans Mertens; Geert Eneman; Naoto Horiguchi; Jeffrey Smith 003; et al. (ESSDERC, 2017)

Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications. - Jeffrey A. Smith; Kai Ni 004; Ram Krishna Ghosh; Jeff Xu; Mustafa Badaroglu; P. R. Chidi Chidambaram; Suman Datta (ESSDERC, 2017)

Sustaining Moore's Law with 3D Chips. - Erik P. DeBenedictis; Mustafa Badaroglu; An Chen; Thomas M. Conte; Paolo A. Gargini (Computer, 2017)

Towards fog-driven IoT eHealth: Promises and challenges of IoT in medicine and healthcare. - Bahar J. Farahani; Farshad Firouzi; Victor I. Chang 001; Mustafa Badaroglu; Nicholas Constant; Kunal Mankodiya (Future Gener. Comput. Syst., 2018)

Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics. - Farshad Firouzi; Amir M. Rahmani; Kunal Mankodiya; Mustafa Badaroglu; Geoff V. Merrett; P. Wong; Bahar J. Farahani (Future Gener. Comput. Syst., 2018)

Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond. - Mustafa Badaroglu (J. Low Power Electron., 2018)

Outlook of device and assembly technologies enabling high-performance mobile computing: IRDS view (invited). - Mustafa Badaroglu (SLIP, 2020)

A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network. - Houman Zahedmanesh; Ivan Ciofi; Odysseas Zografos; Mustafa Badaroglu; Kristof Croes (SLIP, 2021)

System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents. - Houman Zahedmanesh; Ivan Ciofi; Odysseas Zografos; Kristof Croes; Mustafa Badaroglu (IRPS, 2022)