Power, Energy, and Thermal Considerations in SSD-Based I/O Acceleration. - Jie Zhang 048; Mustafa M. Shihab; Myoungsoo Jung (HotStorage, 2014)

OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterization. - Jie Zhang 048; Gieseo Park; Mustafa M. Shihab; David Donofrio; John Shalf; Myoungsoo Jung (ICCD, 2015)

Couture: Tailoring STT-MRAM for Persistent Main Memory. - Mustafa M. Shihab; Jie Zhang 048; Shuwen Gao; Josep Sloan; Myoungsoo Jung (INFLOW@OSDI, 2016)

Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs. - Monir Zaman; Mustafa M. Shihab; Ayse K. Coskun; Yiorgos Makris (PATMOS, 2018)

ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design. - Mustafa M. Shihab; Jie Zhang 048; Myoungsoo Jung; Mahmut T. Kandemir (ACM Trans. Archit. Code Optim., 2018)

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. - Mustafa M. Shihab; Jingxiang Tian; Gaurav Rajavendra Reddy; Bo Hu; William Swartz; Benjamin Carrión Schäfer; Carl Sechen; Yiorgos Makris (DATE, 2019)

Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. - Bo Hu; Jingxiang Tian; Mustafa M. Shihab; Gaurav Rajavendra Reddy; William Swartz; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (ACM Great Lakes Symposium on VLSI, 2019)

Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. - Bo Hu; Mustafa M. Shihab; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (FPT, 2019)

Energy Efficient Power Distribution on Many-Core SoC. - Mustafa M. Shihab; Vishwani D. Agrawal (VLSID, 2019)

CAPE: A cross-layer framework for accurate microprocessor power estimation. - Monir Zaman; Mustafa M. Shihab; Ayse K. Coskun; Yiorgos Makris (Integr., 2019)

An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. - Bo Hu; Mustafa M. Shihab; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (DATE, 2020)

CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric. - Mustafa M. Shihab; Bharath Ramanidharan; Gaurav Rajavendra Reddy; Jingxiang Tian; William Swartz; Carl Sechen; Yiorgos Makris (ISCAS, 2020)

ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric. - Mustafa Munawar Shihab; Bharath Ramanidharan; Suraag Sunil Tellakula; Gaurav Rajavendra Reddy; Jingxiang Tian; Carl Sechen; Yiorgos Makris (VTS, 2020)

Secure Logic Locking with Strain-Protected Nanomagnet Logic. - Naimul Hassan; Alexander J. Edwards; Dhritiman Bhattacharya; Mustafa M. Shihab; Varun Venkat; Peng Zhou; Xuan Hu 002; Shamik Kundu; Abraham Peedikayil Kuruvila; Kanad Basu; Jayasimha Atulasimha; Yiorgos Makris; et al. (DAC, 2021)

Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits. - Alexander J. Edwards; Naimul Hassan; Dhritiman Bhattacharya; Mustafa M. Shihab; Peng Zhou; Xuan Hu 002; Jayasimha Atulasimha; Yiorgos Makris; Joseph S. Friedman (DATE, 2022)

FuncTeller: How Well Does eFPGA Hide Functionality? - Zhaokun Han; Mohammed Shayan; Aneesh Dixit; Mustafa M. Shihab; Yiorgos Makris; Jeyavijayan Rajendran (USENIX Security Symposium, 2023)

A TRAP for SAT: On the Imperviousness of a Transistor-Level Programmable Fabric to Satisfiability-Based Attacks. - Aric Fowler; Mohammed Shayan; Mustafa M. Shihab; Thomas Broadfoot; Peter Beerel; Carl Sechen; Yiorgos Makris (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

Physically Secure Logic Locking With Nanomagnet Logic. - Alexander J. Edwards; Naimul Hassan; Jared Arzate; Alexander N. Chin; Dhritiman Bhattacharya; Mustafa M. Shihab; Peng Zhou; Xuan Hu 002; Jayasimha Atulasimha; Yiorgos Makris; Joseph S. Friedman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)