Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models. - Muthupandian Cheralathan; Esteban Contreras; Joaquín Alvarado; Antonio Cerdeira; Giuseppe Iannaccone; Enrico Sangiorgi; Benjamín Iñíguez (Microelectron. J., 2013)

Projected Tolerances of Carbon Nanotube Current-Mode Logic to Process Variability. - Muthupandian Cheralathan; Martin Claus; Stefan Blawid (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Parameter Extraction from SCLC Transport Mechanism in MIS RRAM Structures. - Muthupandian Cheralathan; Piotr Wisniewski 002; Romuald B. Beck (MIXDES, 2024)