A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations. - Insik Yoon; Muya Chang; Kai Ni 004; Matthew Jerry; Samantak Gangopadhyay; Gus Henry Smith; Tomer Hamam; Vijayakrishan Narayanan; Justin Romberg; Shih-Lien Lu; Suman Datta; Arijit Raychowdhury (DRC, 2018)

Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations. - Muya Chang; Li-Hsiang Lin; Justin Romberg; Arijit Raychowdhury (CICC, 2019)

Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture. - Muya Chang; Samantak Gangopadhyay; Tomer Hamam; Justin Romberg; Arijit Raychowdhury (ICASSP, 2019)

A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics. - Ningyuan Cao; Muya Chang; Arijit Raychowdhury (ISSCC, 2019)

27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation. - Debayan Das; Josef Danial; Anupam Golder; Nirmoy Modak; Shovan Maity; Baibhab Chatterjee; Dong-Hyun Seo; Muya Chang; Avinash Varna 001; Harish Krishnamurthy; Sanu Mathew; Santosh Ghosh; et al. (ISSCC, 2020)

A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller. - Ningyuan Cao; Baibhab Chatterjee; Minxiang Gong; Muya Chang; Shreyas Sen; Arijit Raychowdhury (VLSI Circuits, 2020)

A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics. - Ningyuan Cao; Muya Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2020)

OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers. - Muya Chang; Li-Hsiang Lin; Justin Romberg; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2020)

A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (CICC, 2021)

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2021)

EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. - Debayan Das; Josef Danial; Anupam Golder; Nirmoy Modak; Shovan Maity; Baibhab Chatterjee; Dong-Hyun Seo; Muya Chang; Avinash Varna 001; Harish K. Krishnamurthy; Sanu Mathew; Santosh Ghosh; et al. (IEEE J. Solid State Circuits, 2021)

A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update. - Minxiang Gong; Ningyuan Cao; Muya Chang; Arijit Raychowdhury (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Hardware Dynamical System for Solving Optimization Problems. - Muya Chang (2021)

An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems. - Muya Chang; Xunzhao Yin; Zoltán Toroczkai; Xiaobo Hu 001; Arijit Raychowdhury (CICC, 2022)

Stochastic Mixed-Signal Circuit Design for In-Sensor Privacy. - Ningyuan Cao; Jianbo Liu; Boyang Cheng; Muya Chang (ICCAD, 2022)

A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. - Muya Chang; Samuel D. Spetalnick; Brian Crafton; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2022)

A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. - Samuel D. Spetalnick; Muya Chang; Brian Crafton; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2022)

A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller. - Ningyuan Cao; Baibhab Chatterjee; Jianbo Liu; Boyang Cheng; Minxiang Gong; Muya Chang; Shreyas Sen; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2022)

A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2022)

A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2022)

A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads. - Mustafa Fayez Ali; Indranil Chakraborty; Sakshi Choudhary; Muya Chang; Dong Eun Kim; Arijit Raychowdhury; Kaushik Roy 001 (CICC, 2023)

Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem. - Ashwin Sanjay Lele; Muya Chang; Samuel D. Spetalnick; Brian Crafton; Arijit Raychowdhury; Yan Fang (DAC, 2023)

Privacy-by-Sensing with Time-domain Differentially-Private Compressed Sensing. - Jianbo Liu; Boyang Cheng; Pengyu Zeng; Steven Davis; Muya Chang; Ningyuan Cao (DATE, 2023)

Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. - Ashwin Sanjay Lele; Muya Chang; Samuel Spetalnick; Yan Fang; Brian Crafton; Shota Konno; Arijit Raychowdhury (ISCAS, 2023)

A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. - Muya Chang; Ashwin Sanjay Lele; Samuel D. Spetalnick; Brian Crafton; Shota Konno; Zishen Wan; Ashwin Bhat; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2023)

A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. - Samuel D. Spetalnick; Muya Chang; Shota Konno; Brian Crafton; Ashwin Sanjay Lele; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (VLSI Technology and Circuits, 2023)

A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC. - Kaushik Bhattacharyya; Minxiang Gong; Muya Chang; Xin Zhang 025; Arijit Raychowdhury (ISCAS, 2024)

30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2024)

A 28nm Approximate / Binary 6T CAM for Sequence Alignment. - Brian Crafton; Samuel D. Spetalnick; Muya Chang; Arijit Raychowdhury (VLSI Technology and Circuits, 2024)

E-Gaze: Gaze Estimation With Event Camera. - Nealson Li; Muya Chang; Arijit Raychowdhury (IEEE Trans. Pattern Anal. Mach. Intell., 2024)

A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. - Ashwin Sanjay Lele; Muya Chang; Samuel D. Spetalnick; Brian Crafton; Shota Konno; Zishen Wan; Ashwin Bhat; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2024)

In-Situ Privacy via Mixed-Signal Perturbation and Hardware-Secure Data Reversibility. - Steven Davis; Jianbo Liu; Boyang Cheng; Muya Chang; Ningyuan Cao (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2025)