Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. - Muzaffer O. Simsir; Srihari Cadambi; Franjo Ivancic; Martin Rötteler; Niraj K. Jha (VLSI Design, 2008)

Thermal characterization of BIST, scan design and sequential test methodologies. - Muzaffer O. Simsir; Niraj K. Jha (ITC, 2009)

A hybrid nano-CMOS architecture for defect and fault tolerance. - Muzaffer O. Simsir; Srihari Cadambi; Franjo Ivancic; Martin Rötteler; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2009)

Fault modeling for FinFET circuits. - Muzaffer O. Simsir; Ajay N. Bhoj; Niraj K. Jha (NANOARCH, 2010)

NanoV: Nanowire-based VLSI design. - Muzaffer O. Simsir; Niraj K. Jha (NANOARCH, 2010)