Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies. - Myeong-Eun Hwang; Arijit Raychowdhury; Kaushik Roy 001 (ISCAS (3), 2004)

Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies. - Myeong-Eun Hwang; Arijit Raychowdhury; Kairshik Roy 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling. - Myeong-Eun Hwang; Tamer Cakici; Kaushik Roy 001 (DATE, 2007)

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. - Myeong-Eun Hwang; Seong-Ook Jung; Kaushik Roy 001 (ISLPED, 2007)

A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology. - Myeong-Eun Hwang; Kaushik Roy 001 (CICC, 2008)

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. - Myeong-Eun Hwang; Seong-Ook Jung; Kaushik Roy 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling. - Myeong-Eun Hwang; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling. - Myeong-Eun Hwang; Sungoh Kwon (J. Electr. Comput. Eng., 2016)