An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. - Zbigniew Kalbarczyk; Janak H. Patel; Myeong S. Lee; Ravishankar K. Iyer (VLSI Design, 1999)

Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation. - Zbigniew Kalbarczyk; Ravishankar K. Iyer; Gregory L. Ries; Jaqdish U. Patel; Myeong S. Lee; Yuxiao Xiao (IEEE Trans. Software Eng., 1999)