647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. - Benjamin Stefan Devlin; MyeongGyu Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2009)

Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. - MyeongGyu Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ACM Great Lakes Symposium on VLSI, 2009)