Multi-thread VLIW processor architecture for HDTV decoding. - Hansoo Kim; Woo-Seung Yang; Myoung-Cheol Shin; Seung-Jai Min; Seong-Ok Bae; In-Cheol Park (CICC, 2000)

Optimal down-conversion in compressed DCT domain with minimal operations. - Myoung-Cheol Shin; In-Cheol Park (VCIP, 2000)

An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. - Myoung-Cheol Shin; Se-Hyeon Kang; In-Cheol Park (ICCD, 2001)

Area-efficient digital baseband module for Bluetooth wireless communications. - Myoung-Cheol Shin; Seong-Il Park; Sung-Won Lee 005; Se-Hyeon Kang; In-Cheol Park (ISCAS (5), 2002)

Processor-based turbo interleaver for multiple third-generation wireless standards. - Myoung-Cheol Shin; In-Cheol Park (IEEE Commun. Lett., 2003)

SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. - Myoung-Cheol Shin; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2007)