A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure. - Ki-Tae Park; Doo-Gon Kim; Soonwook Hwang; Myounggon Kang; Hoosung Cho; Youngwook Jeong; Yong-Il Seo; Jae-hoon Jang; Hansoo Kim; Soon-Moon Jung; Yeong-Taek Lee; Changhyun Kim; et al. (ISSCC, 2008)

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories. - Ki-Tae Park; Myounggon Kang; Doogon Kim; Soonwook Hwang; Byung Yong Choi; Yeong-Taek Lee; Changhyun Kim; Kinam Kim (IEEE J. Solid State Circuits, 2008)

A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure. - Ki-Tae Park; Myounggon Kang; Soonwook Hwang; Doo-Gon Kim; Hoosung Cho; Youngwook Jeong; Yong-Il Seo; Jae-hoon Jang; Hansoo Kim; Yeong-Taek Lee; Soon-Moon Jung; Changhyun Kim (IEEE J. Solid State Circuits, 2009)

A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory. - Myounggon Kang; Ki-Tae Park; Youngsun Song; Sungsoo Lee; Yunheub Song; Youngho Lim (IEICE Trans. Electron., 2010)

Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory. - Youngsun Song; Ki-Tae Park; Myounggon Kang; Yunheub Song; Sungsoo Lee; Youngho Lim; Kang-Deog Suh (IEICE Trans. Electron., 2010)

Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories. - Ki-Tae Park; Youngsun Song; Myounggon Kang; Sungsoo Lee; Youngho Lim; Kang-Deog Suh; Chilhee Chung (IEEE J. Solid State Circuits, 2010)

The novel SCR-based ESD protection with low triggering and high holding voltages. - Myounggon Kang; Ki-Whan Song; Byung-Gook Park; Hyungcheol Shin (Microelectron. J., 2011)

Investigation of capture and emission dependence between individual traps from complex random telegraph signal noise analysis. - Younghwan Son; Yoon Kim; Myounggon Kang (IEICE Electron. Express, 2017)

Characterization of oxide trap density with the charge pumping technique in dual-layer gate oxide. - Younghwan Son; Yoon Kim; Myounggon Kang (IEICE Electron. Express, 2017)

A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems. - Duckhoon Ro; Changhong Min; Myounggon Kang; Ik Joon Chang; Hyung-Min Lee (Sensors, 2020)

Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET). - Sueyeon Kim; Insoo Choi; Sangki Cho; Myounggon Kang; Seungjae Baik; Changho Ra; Jongwook Jeon (IEEE Access, 2023)

Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning. - Jun Hui Park; Jung Nam Kim; Seonhaeng Lee; Gang-Jun Kim; Namhyun Lee; Rock-Hyun Baek; Dae Hwan Kim; Changhyun Kim; Myounggon Kang; Yoon Kim (IEEE Access, 2024)