Performance-controllable shared cache architecture for multi-core soft real-time systems. - Myoungjun Lee; Soontae Kim (ICCD, 2013)

MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems. - Jungwoo Park; Myoungjun Lee; Soontae Kim; Minho Ju; Jeongkyu Hong (ACM Trans. Archit. Code Optim., 2019)

Time-sensitivity-aware shared cache architecture for multi-core embedded systems. - Myoungjun Lee; Soontae Kim (J. Supercomput., 2019)