A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability. - Dirk Reese; Eric Chun; Sammy Cheung; Edmond Lau; Michael Chu; Gwen Liang; Nghia Van Tran; Brad Vest; Richard Smolen; Minchang Liang; Seshan Sekariapuram; Behzad Nouban; et al. (CICC, 1998)

A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming. - Brad Vest; Gwen Liang; Mark Chan; Eric Chun; Mark Fiester; Weiying Ding; Edmond Lau; Guu Lin; Behzad Nouban; Dirk Reese; Mian Smith; Nghia Tran; et al. (CICC, 1999)

Cyclone ™: a low-cost, high-performance FPGA. - Paul Leventis; Mark Chan; Michael Chan; David M. Lewis; Behzad Nouban; Giles Powell; Brad Vest; Myron Wong; Renxin Xia; John Costello (CICC, 2003)