High Performance VLSI Architecture Design for H.264 CAVLC Decoder. - Mythri Alle; Jayanta Biswas; S. K. Nandy 001 (ASAP, 2006)

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. - A. N. Satrawala; Keshavan Varadarajan; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (FPL, 2007)

Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. - Adarsha Rao; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ASAP, 2008)

Synthesis of application accelerators on Runtime Reconfigurable Hardware. - Mythri Alle; Keshavan Varadarajan; Ramesh C. Ramesh; Joseph Nimmy; Alexander Fell; Adarsha Rao; S. K. Nandy 001; Ranjani Narayan (ASAP, 2008)

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. - Joseph Nimmy; C. Ramesh Reddy; Keshavan Varadarajan; Mythri Alle; Alexander Fell; S. K. Nandy 001; Ranjani Narayan (ASAP, 2008)

Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network. - Ganesh Garga; Mythri Alle; Keshavan Varadarajan; S. K. Nandy 001; H. S. Jamadagni (SoC, 2008)

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. - Mythri Alle; Keshavan Varadarajan; Alexander Fell; S. K. Nandy 001; Ranjani Narayan (ARC, 2009)

An Input Triggered Polymorphic ASIC for H.264 Decoding. - Adarsha Rao; Mythri Alle; Sainath V; Reyaz Shaik; Rajashekhar Chowhan; Sreeramula Sankaraiah; Sravanthi Mantha; S. K. Nandy 001; Ranjani Narayan (ASAP, 2009)

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. - Alexander Fell; Mythri Alle; Keshavan Varadarajan; Prasenjit Biswas; Saptarsi Das; Jugantor Chetia; S. K. Nandy 001; Ranjani Narayan (CASES, 2009)

REDEFINE: Runtime reconfigurable polymorphic ASIC. - Mythri Alle; Keshavan Varadarajan; Alexander Fell; C. Ramesh Reddy; Joseph Nimmy; Saptarsi Das; Prasenjit Biswas; Jugantor Chetia; Adarsha Rao; S. K. Nandy 001; Ranjani Narayan (ACM Trans. Embed. Comput. Syst., 2009)

Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. - Ratna Krishnamoorthy; Keshavan Varadarajan; Ganesh Garga; Mythri Alle; S. K. Nandy 001; Ranjani Narayan; Masahiro Fujita (CASES, 2010)

Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. - Prasenjit Biswas; Pramod P. Udupa; Rajdeep Mondal; Keshavan Varadarajan; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ISVLSI, 2010)

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. - Prasenjit Biswas; Keshavan Varadarajan; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2010)

Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. - N. Thambi Prashank; M. Prasadarao; Avinaba Dutta; Keshavan Varadarajan; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2010)

Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. - Ratna Krishnamoorthy; Keshavan Varadarajan; Masahiro Fujita; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ARC, 2011)

Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. - Ratna Krishnamoorthy; Saptarsi Das; Keshavan Varadarajan; Mythri Alle; Masahiro Fujita; Soumitra Kumar Nandy; Ranjani Narayan (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Runtime dependency analysis for loop pipelining in high-level synthesis. - Mythri Alle; Antoine Morvan; Steven Derrien (DAC, 2013)

GeCoS: A framework for prototyping custom hardware design flows. - Antoine Floch; Tomofumi Yuki; Ali El Moussawi; Antoine Morvan; Kevin J. M. Martin; Maxime Naullet; Mythri Alle; Ludovic L'Hours; Nicolas Simon; Steven Derrien; François Charot; Christophe Wolinski; et al. (SCAM, 2013)