PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC. - K. Rahimunnisa; P. Karthigaikumar; N. Anitha Christy; S. Suresh Kumar; J. Jayakumar (Central Eur. J. Comput. Sci., 2013)

PSP CO2: An Efficient Hardware Architecture for AES Algorithm for High Throughput. - P. Karthigaikumar; N. Anitha Christy; N. M. Siva Mangai (Wirel. Pers. Commun., 2015)