An efficient delay estimation model for high speed VLSI interconnects. - Mummaneni Kavicharan; Nukala Suryanarayana Murthy; N. Bheema Rao (ICACCI, 2013)

Efficient delay and Crosstalk estimation Models for Current-mode High Speed interconnects under Ramp input. - Mummaneni Kavicharan; Nukala Suryanarayana Murthy; N. Bheema Rao (J. Circuits Syst. Comput., 2014)

Power gating Technique using FinFET for Minimization of sub-Threshold Leakage Current. - K. Keerti Kumar; N. Bheema Rao (J. Circuits Syst. Comput., 2014)

Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects. - Mummaneni Kavicharan; Nukala Suryanarayana Murthy; N. Bheema Rao; Addanki Prathima (Circuits Syst. Signal Process., 2016)

A FinFET based 2nd-Order Fully Differential Passive Sigma Delta Modulator for Low Power ADC. - K. Sarangam; N. Bheema Rao (ICCCNT, 2020)

Stacked Multi-layer Zig-Zag On-chip Inductor. - Manchala Naveen; N. Bheema Rao (iSES, 2022)