Timing analysis for digital fault simulation using assignable delays. - Edward W. Thompson; Stephen A. Szygenda; N. Billawala; R. Pierce (DAC, 1974)

The software engineering technique of data hiding as applied to multi-level model implementation of logical devices in digital simulation. - Edward W. Thompson; N. Billawala (DAC, 1975)

A Data Structure and Drive Mechanism for a Table-Driven Simulation System Employing Multilevel Structural Representations of Digital Systems. - N. Billawala; Stephen A. Szygenda; Ewald W. Thomson (ICSE, 1976)