Low power, variable resolution pipelined analog to Digital converter with sub flash architecture. - Mahesh Kumar Adimulam; Krishna Kumar Movva; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; Mandalika B. Srinivas (APCCAS, 2010)

A low power, variable resolution two-step flash ADC. - Mahesh Kumar Adimulam; Krishna Kumar Movva; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ACM Great Lakes Symposium on VLSI, 2010)

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. - Mahesh Kumar Adimulam; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISVLSI, 2010)

A Unified Architecture for BCD and Binary Adder/Subtractor. - Chetan Kumar V.; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (DSD, 2011)

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. - P. Sai Phaneendra; Chetan Vudadha; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISCIT, 2011)

A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter. - Mahesh Kumar Adimulam; Krishna Kumar Movva; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISED, 2011)

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. - Chetan Kumar V.; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISED, 2011)

A Prefix Based Reconfigurable Adder. - Chetan Kumar V.; Sai Phaneendra P.; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISVLSI, 2011)

A Modified Twin Precision Multiplier with 2D Bypassing Technique. - Syed Ershad Ahmed; Sibi Abraham; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISED, 2012)

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. - Chetan Vudadha; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; Mandalika B. Srinivas (ISVLSI, 2012)

Design of Prefix-Based Optimal Reversible Comparator. - Chetan Vudadha; P. Sai Phaneendra; Sreehari Veeramachaneni; Syed Ershad Ahmed; N. Moorthy Muthukrishnan; Mandalika B. Srinivas (ISVLSI, 2012)

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. - Chetan Vudadha; Goutham Makkena; M. Venkata Swamy Nayudu; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (VLSI Design, 2012)

Comparison of Voltage Charging Techniques to Increase the Life of Lead Acid Batteries. - Madhuri Bayya; U. M. Rao; BVVSN Prabhakar Rao; N. Moorthy Muthukrishnan (iSES, 2018)