VLSI circuit reconstruction from mask topology. - N. P. van der Meijs; J. T. Fokkema (Integr., 1984)

An Efficient Finite Element Method for Submicron IC Capacitance Extraction. - N. P. van der Meijs; Arjan J. van Genderen (DAC, 1989)

Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures. - Arjan J. van Genderen; N. P. van der Meijs (ICCAD, 1993)

Delayed Frontal Solution for Finite-Element Based Resistance Extraction. - N. P. van der Meijs; Arjan J. van Genderen (DAC, 1995)

Extraction of circuit models for substrate cross-talk. - T. Smedes; N. P. van der Meijs; Arjan J. van Genderen (ICCAD, 1995)

Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. - Frederik Beeftink; Arjan J. van Genderen; N. P. van der Meijs (ICCD, 1995)

Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency. - P. J. H. Elias; N. P. van der Meijs (DAC, 1996)

Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction. - Arjan J. van Genderen; N. P. van der Meijs (DAC, 1996)

Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction. - P. J. H. Elias; N. P. van der Meijs (ED&TC, 1996)

Fast Computation of Substrate Resistances in Large Circuits. - Arjan J. van Genderen; N. P. van der Meijs; T. Smedes (ED&TC, 1996)

Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. - N. P. van der Meijs; T. Smedes (ICCAD, 1996)

Cartesian multipole based numerical integration for 3D capacitance extraction. - U. Geigenmüller; N. P. van der Meijs (ED&TC, 1997)

Virtual screening: a step towards a sparse partial inductance matrix. - A. J. Dammers; N. P. van der Meijs (ICCAD, 1999)

Combined BEM/FEM substrate resistance modeling. - Eelco Schrik; N. P. van der Meijs (DAC, 2002)

Theoretical and practical validation of combined BEM/FEM substrate resistance modeling. - Eelco Schrik; Patrick M. Dewilde; N. P. van der Meijs (ICCAD, 2002)

Analytic model for area and power constrained optimal repeater insertion. - Giuseppe S. Garcea; Nick van der Meijs; Ralph H. J. M. Otten (ESSCIRC, 2003)

Simultaneous Analytic Area and Power Optimization for Repeater Insertion. - Giuseppe S. Garcea; N. P. van der Meijs; Ralph H. J. M. Otten (ICCAD, 2003)

Statistically Aware Buffer Planning. - Giuseppe S. Garcea; N. P. van der Meijs; Kees-Jan van der Kolk; Ralph H. J. M. Otten (DATE, 2004)

Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors. - Yu Bi; Kees-Jan van der Kolk; Nick van der Meijs (CICC, 2009)

A Radix 22 based parallel pipeline FFT processor for MB-OFDM UWB system. - Nuo Li; Nick van der Meijs (SoCC, 2009)

Noise analysis of non-linear dynamic integrated circuits. - Amir Zjajo; Qin Tang; Michel Berkelaar; Nick van der Meijs (CICC, 2010)

RDE-based transistor-level gate simulation for statistical static timing analysis. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (DAC, 2010)

Digital cartesian feedback linearization of switched mode power amplifiers. - Alejandro Viteri; Amir Zjajo; Thijmen Hamoen; Nick van der Meijs (ICECS, 2010)

Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (PATMOS, 2010)

Statistical Moment Estimation of Delay and Power in Circuit Simulation. - Ashish Nigam; Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (J. Low Power Electron., 2010)

Efficient sensitivity-based capacitance modeling for systematic and random geometric variations. - Yu Bi; Pieter Harpe; N. P. van der Meijs (ASP-DAC, 2011)

Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique. - Yu Bi; Simon de Graaf; Nick van der Meijs (CICC, 2011)

Fast statistical analysis of RC nets subject to manufacturing variabilities. - Yu Bi; Kees-Jan van der Kolk; Jorge Fernandez Villena; Luís Miguel Silveira; Nick van der Meijs (DATE, 2011)

Pseudo circuit model for representing uncertainty in waveforms. - Ashish Nigam; Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (DATE, 2011)

A 26 μ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios. - Pieter Harpe; Cui Zhou; Yu Bi; N. P. van der Meijs; Xiaoyan Wang 002; Kathleen Philips; Guido Dolmans; Harmke de Groot (IEEE J. Solid State Circuits, 2011)

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs. - Amir Zjajo; Qin Tang; Michel Berkelaar; José Pineda de Gyvez; Alessandro Di Bucchianico; Nick van der Meijs (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Crosstalk-aware statistical interconnect delay calculation. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (ASP-DAC, 2012)

Transistor-level gate model based statistical timing analysis considering correlations. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (DATE, 2012)

A 11 µW 0°C-160°C temperature sensor in 90 nm CMOS for adaptive thermal monitoring of VLSI circuits. - Amir Zjajo; Nick van der Meijs; René van Leuken 001 (ISCAS, 2012)

Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method. - Amir Zjajo; Nick van der Meijs; Rene van Leuken 001 (ISQED, 2012)

Direct Statistical Simulation of Timing Properties in Sequential Circuits. - Javier Rodríguez; Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (PATMOS, 2012)

Balanced stochastic truncation of coupled 3D interconnect. - Amir Zjajo; Nick van der Meijs; Rene van Leuken 001 (ICICDT, 2013)

A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter. - Jan A. Angevare; Kristof Blutman; Amir Zjajo; Nick van der Meijs (NORCHIP, 2013)

Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits. - Amir Zjajo; Nick van der Meijs; Rene van Leuken 001 (J. Low Power Electron., 2013)

A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS. - Kristof Blutman; Jan A. Angevare; Amir Zjajo; Nick van der Meijs (ISCAS, 2014)

Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron. - Amir Zjajo; Nick van der Meijs; Rene van Leuken 001 (ISIC, 2014)

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver. - Qin Tang; Javier Rodríguez; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Considering Crosstalk Effects in Statistical Timing Analysis. - Qin Tang; Amir Zjajo; Michel Berkelaar; Nick van der Meijs (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC. - Amir Zjajo; Nick van der Meijs; Rene van Leuken 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)