A Reconfigurable Platform for Real-Time Embedded Video Image Processing. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (FPL, 2003)

A Structured System Methodology for FPGA Based System-on-A-Chip Design. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (FCCM, 2004)

A Structured Methodology for System-on-an-FPGA Design. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (FPL, 2004)

Modular Partial Reconfiguration in Virtex FPGAs. - N. Pete Sedcole; Brandon Blodget; Tobias Becker; James Anderson; Patrick Lysaght (FPL, 2005)

On-FPGA Communication Architectures and Design Factors. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (FPL, 2006)

Within-die delay variability in 90nm FPGAs and beyond. - N. Pete Sedcole; Peter Y. K. Cheung (FPT, 2006)

On-Chip Communication in Run-Time Assembled Reconfigurable Systems. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (ICSAMOS, 2006)

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. - N. Pete Sedcole; Peter Y. K. Cheung (FPGA, 2007)

Self-characterization of Combinatorial Circuit Delays in FPGAs. - Justin S. J. Wong; N. Pete Sedcole; Peter Y. K. Cheung (FPT, 2007)

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk; Kai-Pui Lam (NOCS, 2007)

Run-Time Integration of Reconfigurable Video Processing Systems. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2007)

High-throughput interconnect wave-pipelining for global communication in FPGAs. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (FPGA, 2008)

Measuring and modeling FPGA clock variability. - N. Pete Sedcole; Justin S. J. Wong; Peter Y. K. Cheung (FPGA, 2008)

Fault tolerant methods for reliability in FPGAs. - Edward A. Stott; N. Pete Sedcole; Peter Y. K. Cheung (FPL, 2008)

Combating process variation on FPGAS with a precise at-speed delay measurement method. - Justin S. J. Wong; Peter Y. K. Cheung; N. Pete Sedcole (FPL, 2008)

Wave-pipelined signaling for on-FPGA communication. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (FPT, 2008)

Modelling and compensating for clock skew variability in FPGAs. - N. Pete Sedcole; Justin S. J. Wong; Peter Y. K. Cheung (FPT, 2008)

A transition probability based delay measurement method for arbitrary circuits on FPGAs. - Justin S. J. Wong; N. Pete Sedcole; Peter Y. K. Cheung (FPT, 2008)

Characterisation of FPGA Clock Variability. - N. Pete Sedcole; Justin S. J. Wong; Peter Y. K. Cheung (ISVLSI, 2008)

Implementation of Wave-Pipelined Interconnects in FPGAs. - Terrence S. T. Mak; Crescenzo D'Alessandro; N. Pete Sedcole; Peter Y. K. Cheung; Alexandre Yakovlev; Wayne Luk (NOCS, 2008)

Global interconnections in FPGAs: modeling and performance analysis. - Terrence S. T. Mak; Crescenzo D'Alessandro; N. Pete Sedcole; Peter Y. K. Cheung; Alexandre Yakovlev; Wayne Luk (SLIP, 2008)

Interconnection lengths and delays estimation for communication links in FPGAs. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (SLIP, 2008)

Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. - N. Pete Sedcole; Peter Y. K. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2008)

Compensating for variability in FPGAs by re-mapping and re-placement. - N. Pete Sedcole; Edward A. Stott; Peter Y. K. Cheung (FPL, 2009)

Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. - Li Wang; Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung (ISCAS, 2009)

Self-Measurement of Combinatorial Circuit Delays in FPGAs. - Justin S. J. Wong; N. Pete Sedcole; Peter Y. K. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2009)

Degradation in FPGAs: measurement and modelling. - Edward A. Stott; Justin S. J. Wong; N. Pete Sedcole; Peter Y. K. Cheung (FPGA, 2010)

Fault tolerance and reliability in field-programmable gate arrays. - Edward A. Stott; N. Pete Sedcole; Peter Y. K. Cheung (IET Comput. Digit. Tech., 2010)

Wave-pipelined intra-chip signaling for on-FPGA communications. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (Integr., 2010)