A scheme for data compression in supercomputers. - Mostafa A. Bassiouni; N. Ranganathan; Amar Mukherjee (SC, 1988)

Software and Hardware Enhancement of Arithmetic Coding. - Mostafa A. Bassiouni; N. Ranganathan; Amar Mukherjee (SSDBM, 1988)

A VLSI architecture for computing scale space. - N. Ranganathan; Mubarak Shah (Comput. Vis. Graph. Image Process., 1988)

Adaptive and pipelined VLSI designs for tree-based codes. - Amar Mukherjee; N. Ranganathan; Mostafa A. Bassiouni (ICCD, 1989)

On Software and Hardware Techniques of Data Engineering. - Mostafa A. Bassiouni; Amar Mukherjee; N. Ranganathan (ICDE, 1989)

A VLSI system for difference picture-based motion analysis. - N. Ranganathan; Rajiv Mehrotra (TAI, 1989)

Enhancing arithmetic and tree-based coding. - Mostafa A. Bassiouni; Amar Mukherjee; N. Ranganathan (Inf. Process. Manag., 1989)

SAP: design of a systolic array processor for computation in vision. - Sanjay Nichani; N. Ranganathan (ICCD, 1990)

Fast spatiotemporal filters. - K. R. Namaduri; Rajiv Mehrotra; N. Ranganathan (ICPR (2), 1990)

A VLSI architecture for difference picture-based dynamic scene analysis. - N. Ranganathan; Rajiv Mehrotra (ICPR (2), 1990)

Effect of Data Compression Hardware on the Performance of a Relational Database Machine. - N. Ranganathan; Hassan N. Srinidhi (PARBASE, 1990)

A parallel architecture for data compression. - Selwyn Henriques; N. Ranganathan (SPDP, 1990)

Corner detection. - Rajiv Mehrotra; Sanjay Nichani; Nagarajan Ranganathan (Pattern Recognit., 1990)

An architecture to implement multiresolution. - N. Ranganathan; Rajiv Mehrotra; Kameswara Rao Namuduri (ICASSP, 1991)

A VLSI architecture for dynamic scene analysis. - N. Ranganathan; Rajiv Mehrotra (CVGIP Image Underst., 1991)

A VLSI architecture for a half-edge-based corner detector. - N. Ranganathan; Sanjay Nichani; Rajiv Mehrotra (Mach. Vis. Appl., 1991)

MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. - Amar Mukherjee; Jeffrey W. Flieder; N. Ranganathan (ICCD, 1992)

Edge detection models based on Gabor filters. - Kameswara Rao Namuduri; Rajiv Mehrotra; N. Ranganathan (ICPR (3), 1992)

SIBA: a VLSI systolic array chip for image processing. - Minesh I. Patel; Patrick McCabe; N. Ranganathan (ICPR (4), 1992)

A VLSI hardware accelerator for dynamic time warping. - V. K. Sundaresan; Sanjay Nichani; N. Ranganathan; Ravi Sankar (ICPR (4), 1992)

A VLSI architecture for hierarchical scene matching. - R. Venkatesan; Raghu Sastry; N. Ranganathan (ICPR (4), 1992)

A Systolic Algorithm and Architecture for Galois Field Arithmetic. - Mario Kovac; N. Ranganathan; M. Varanasi (IPPS, 1992)

trulla : An Algorithm For Path Planning Among Weighted Regions By Localized Propagations. - Ken Hughes; Alade Tokuta; N. Ranganathan (IROS, 1992)

A CMOS VLSI Chip for Motion Detection. - N. Ranganathan; Rajiv Mehrotra; S. Kurji (VLSI Design, 1992)

A Two-dimensional Systolic Array Processor for Image Processing. - N. Ranganathan; Minesh I. Patel; Patrick McCabe (VLSI Design, 1992)

A VLSI systolic array processor chip for computing joins in a relational database. - N. Ranganathan; K. R. Balaji; Hassan N. Srinidhi (Microprocess. Microsystems, 1992)

Gabor filter-based edge detection. - Rajiv Mehrotra; Kameswara Rao Namuduri; Nagarajan Ranganathan (Pattern Recognit., 1992)

SMAC: A Scene Matching Chip. - N. Ranganathan; Raghu Sastry; Raguveer Venkatesan; Joseph W. Yoder; David C. Keezer (ICCD, 1993)

A Systolic Array for Approximate String Matching. - Raghu Sastry; N. Ranganathan (ICCD, 1993)

A Model for Determining Sensor Confidence. - Ken Hughes; N. Ranganathan (ICRA (2), 1993)

VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. - Raghu Sastry; N. Ranganathan; Ramesh C. Jain (IPPS, 1993)

SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. - Mario Kovac; N. Ranganathan; M. Varanasi (VLSI Design, 1993)

Hardware Algorithms for Polygon Matching. - Raghu Sastry; N. Ranganathan; Horst Bunke (VLSI Design, 1993)

SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm. - Mario Kovac; N. Ranganathan; M. Varanasi (IEEE Trans. Very Large Scale Integr. Syst., 1993)

MARVLE: a VLSI chip for data compression using tree-based codes. - Amar Mukherjee; N. Ranganathan; Jeffrey W. Flieder; Tinku Acharya (IEEE Trans. Very Large Scale Integr. Syst., 1993)

VLSI architectures for polygon recognition. - Raghu Sastry; N. Ranganathan; Horst Bunke (IEEE Trans. Very Large Scale Integr. Syst., 1993)

A VLSI Chip for Template Matching. - N. Ranganathan; Satish Venugopal (ICCD, 1994)

An Efficient VLSI Architecture for Template Matching. - N. Ranganathan; Satish Venugopal (ICPP (1), 1994)

An efficient VLSI architecture for template matching based on moment preserving pattern matching. - N. Ranganathan; Satish Venugopal (ICPR (3), 1994)

A Parallel Algorithm and Architecture for Robot Path Planning. - N. Ranganathan; Bharadwaj Parthasarathy; Ken Hughes (IPPS, 1994)

ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. - Mario Kovac; N. Ranganathan (VLSI Design, 1994)

Modeling Sensor Confidence for Sensor Integration Tasks. - Ken Hughes; N. Ranganathan (Int. J. Pattern Recognit. Artif. Intell., 1994)

VLSI Architectures for Pattern Matching. - N. Ranganathan; Raghu Sastry (Int. J. Pattern Recognit. Artif. Intell., 1994)

Efficient computation of gabor filter based multiresolution responses. - Kameswara Rao Namuduri; Rajiv Mehrotra; Nagarajan Ranganathan (Pattern Recognit., 1994)

A prototype VLSI chip architecture for JPEG image compression. - Mario Kovac; N. Ranganathan; Martin Zagar (ED&TC, 1995)

A systolic algorithm and architecture for image thinning. - N. Ranganathan; K. B. Doreswamy (Great Lakes Symposium on VLSI, 1995)

A VLSI Architecture for Computer the Tree-to-Tree Distance. - Raghu Sastry; N. Ranganathan (HPCA, 1995)

Systolic algorithms for tree pattern matching. - Abdel Ejnioui; N. Ranganathan (ICCD, 1995)

JAGUAR: a high speed VLSI chip for JPEG image compression standard. - Mario Kovac; N. Ranganathan (VLSI Design, 1995)

Conference Reports. - N. Ranganathan; Sharad C. Seth (IEEE Des. Test Comput., 1995)

PMAC: A Polygon Matching Chip. - Raghu Sastry; N. Ranganathan (Int. J. Pattern Recognit. Artif. Intell., 1995)

VLSI Architectures for High-Speed Range Estimation. - Raghu Sastry; N. Ranganathan; Ramesh C. Jain (IEEE Trans. Pattern Anal. Mach. Intell., 1995)

CASM: A VLSI Chip for Approximate String Matching. - Raghu Sastry; N. Ranganathan; Klinton Remedios (IEEE Trans. Pattern Anal. Mach. Intell., 1995)

JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard. - Mario Kovac; N. Ranganathan (Proc. IEEE, 1995)

A lossless image compression algorithm using variable block size segmentation. - Nagarajan Ranganathan; Steve G. Romaniuk; Kameswara Rao Namuduri (IEEE Trans. Image Process., 1995)

A high speed systolic architecture for labeling connected components in an image. - Nagarajan Ranganathan; Rajiv Mehrotra; S. Subramaniam 001 (IEEE Trans. Syst. Man Cybern., 1995)

A VLSI System Architecture For Real-Time Intelligent Decision Making. - Minesh I. Patel; N. Ranganathan (ASAP, 1996)

A linear systolic algorithm and architecture for convex bipartite matching. - Nagarajan Ranganathan; Rajesh Chandra (HiPC, 1996)

A VLSI chip for image compression using variable block size segmentation. - S. B. Aruru; N. Ranganathan; Kameswara Rao Namuduri (ICCD, 1996)

A VLSI array architecture with dynamic frequency clocking. - N. Ranganathan; Narayanan Vijaykrishnan; N. Bhavanishankar (ICCD, 1996)

DFLAP: a dynamic frequency linear array processor. - Narayanan Vijaykrishnan; Nagarajan Ranganathan; N. Bhavanishankar (ICIP (2), 1996)

PANTHER: a parallel neuro-systolic architecture for real-time processing. - Minesh I. Patel; N. Ranganathan (ICNN, 1996)

SIMD algorithms for single link and complete link pattern clustering. - S. Arumugavelu; N. Ranganathan (ICPR, 1996)

A VLSI system architecture for lossless image compression. - S. B. Aruru; N. Ranganathan; Kameswara Rao Namuduri (ICPR, 1996)

SVBS: a high-resolution medical image compression algorithm using slicing with variable block size segmentation. - Kameswara Rao Namuduri; N. Ranganathan; Hooman Rashedi (ICPR, 1996)

Lossless image compression using wavelet decomposition. - Veeru N. Ramaswamy; Kameswara Rao Namuduri; N. Ranganathan (ICPR, 1996)

A dynamic frequency linear array processor for image processing. - N. Ranganathan; N. Bhavanishankar; Narayanan Vijaykrishnan (ICPR, 1996)

An intelligent system architecture for urban traffic control applications. - Minesh I. Patel; N. Ranganathan (SPDP, 1996)

Mapping and parallel implementation of Bayesian belief networks. - Nina Saxena; Sudeep Sarkar; N. Ranganathan (SPDP, 1996)

SUBGEN: a genetic approach for subcircuit extraction. - Narayanan Vijaykrishnan; N. Ranganathan (VLSI Design, 1996)

Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. - Hitoshi Oi; N. Ranganathan (ICCD, 1997)

C3L: A Chip for Connected Component Labeling. - Ashley Rasquinha; N. Ranganathan (VLSI Design, 1997)

Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission. - Ramamurti Chandramouli; N. Ranganathan; Shivaraman J. Ramadoss (Data Compression Conference, 1998)

Object-Oriented Architectural Support for a Java Processor. - Narayanan Vijaykrishnan; N. Ranganathan; Ravi Gadekarla (ECOOP, 1998)

A Methodology for High Level Power Estimation and Exploration. - Vamsi Krishna; N. Ranganathan (Great Lakes Symposium on VLSI, 1998)

A scene-based generalized Markov chain model for VBR video traffic. - Girish Chiruvolu; Tapas K. Das; Ravi Sankar; N. Ranganathan (ICC, 1998)

A simple adaptive wormhole routing algorithm for MIMD systems. - Raju D. Venkataramana; N. Ranganathan (ICCD, 1998)

Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission. - Ramamurti Chandramouli; Sharad Kumar; N. Ranganathan (ICIP (1), 1998)

An adaptive scheme for better utilization with QoS constraints for VBR video traffic in ATM networks. - Girish Chiruvolu; Ravi Sankar; Nagarajan Ranganathan (ISCC, 1998)

Rate control for a video coder using learning automata. - Ramamurti Chandramouli; Sharad Kumar; N. Ranganathan (SMC, 1998)

Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. - Vamsi Krishna; Ramamurti Chandramouli; N. Ranganathan (VLSI Design, 1998)

A VLSI ATM Switch Architecture for VBR Traffic. - Nagarajan Ranganathan; Rajat Anand; Girish Chiruvolu (VLSI Design, 1998)

Adaptive VBR video traffic management for higher utilization of ATM networks. - Girish Chiruvolu; Ravi Sankar; N. Ranganathan (Comput. Commun. Rev., 1998)

A Forum for VLSI Practitioners. - N. Ranganathan (Computer, 1998)

SMAC: A VLSI Architecture for Scene Matching. - N. Ranganathan; Raghu Sastry; Raguveer Venkatesan (Real Time Imaging, 1998)

A generalized sequential sign detector for binary hypothesis testing. - Ramamurti Chandramouli; N. Ranganathan (IEEE Signal Process. Lett., 1998)

A VLSI Architecture for Approximate Tree Matching. - Raghu Sastry; N. Ranganathan (IEEE Trans. Computers, 1998)

Adaptive quantization and fast error-resilient entropy coding for image transmission. - Ramamurti Chandramouli; N. Ranganathan; Shivaraman J. Ramadoss (IEEE Trans. Circuits Syst. Video Technol., 1998)

A linear array processor with dynamic frequency clocking for image processing applications. - Nagarajan Ranganathan; Narayanan Vijaykrishnan; N. Bhavanishankar (IEEE Trans. Circuits Syst. Video Technol., 1998)

Tuning Branch Predictors to Support Virtual Method Invocation in Java. - Narayanan Vijaykrishnan; N. Ranganathan (COOTS, 1999)

Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. - Abdel Ejnioui; N. Ranganathan (FPGA, 1999)

Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata. - Raju D. Venkataramana; N. Ranganathan (Heterogeneous Computing Workshop, 1999)

Context modeling of wavelet coefficients in EZW-based lossless image coding. - Veeraraghavan N. Ramaswamy; Kamesh Namuduri; Nagarajan Ranganathan (ICASSP, 1999)

Context based lossless intraframe coding of video sequence using embedded zerotree wavelets. - Veeru N. Ramaswamy; Kameswara Rao Namuduri; N. Ranganathan (ISCAS (4), 1999)

A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems. - Raju D. Venkataramana; N. Ranganathan (SAC, 1999)

Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. - Vamsi Krishna; N. Ranganathan; Narayanan Vijaykrishnan (VLSI Design, 1999)

Computing the bivariate Gaussian probability integral. - Ramamurti Chandramouli; N. Ranganathan (IEEE Signal Process. Lett., 1999)

Performance analysis of wavelets in embedded zerotree-based lossless image coding schemes. - Veeru N. Ramaswamy; N. Ranganathan; Kameswara Rao Namuduri (IEEE Trans. Signal Process., 1999)

Computation of lower bounds for switching activity using decision theory. - Vamsi Krishna; Ramamurti Chandramouli; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A tree-matching chip. - Vamsi Krishna; N. Ranganathan; Abdel Ejnioui (IEEE Trans. Very Large Scale Integr. Syst., 1999)

New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems. - Raju D. Venkataramana; N. Ranganathan (Heterogeneous Computing Workshop, 2000)

Design Partitioning on Single-Chip Emulation Systems. - Abdel Ejnioui; N. Ranganathan (VLSI Design, 2000)

Routing on Switch Matrix Multi-FPGA Systems. - Abdel Ejnioui; N. Ranganathan (VLSI Design, 2000)

CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. - Vamsi K. Srikantam; N. Ranganathan; Srikanth Srinivasan 002 (VLSI Design, 2000)

VBR video traffic management using a predictor-based architecture. - Girish Chiruvolu; Ravi Sankar; Nagarajan Ranganathan (Comput. Commun., 2000)

Utilization of cache area in on-chip multiprocessor. - Hitoshi Oi; N. Ranganathan (Microprocess. Microsystems, 2000)

Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. - Sanjukta Bhanja; N. Ranganathan (DAC, 2001)

Average Power in Digital CMOS Circuits using Least Square Estimation. - Ashok K. Murugavel; N. Ranganathan; Ramamurti Chandramouli; Srinath Chavali (VLSI Design, 2001)

Context-based lossless image coding using EZW framework. - Veeru N. Ramaswamy; Kameswara Rao Namuduri; N. Ranganathan (IEEE Trans. Circuits Syst. Video Technol., 2001)

An intelligent system for failure detection and control in an autonomous underwater vehicle. - N. Ranganathan; Minesh I. Patel; R. Sathyamurthy (IEEE Trans. Syst. Man Cybern. Part A, 2001)

A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. - Abdel Ejnioui; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2001)

IDUTC: an intelligent decision-making system for urban traffic-control applications. - Minesh I. Patel; N. Ranganathan (IEEE Trans. Veh. Technol., 2001)

A VLSI Architecture for Object Recognition Using Tree Matching. - K. Sitaraman; N. Ranganathan; Abdel Ejnioui (ASAP, 2002)

Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. - Sanjukta Bhanja; N. Ranganathan (ICCD, 2002)

Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. - Ashok K. Murugavel; N. Ranganathan (ISLPED, 2002)

Datapath Scheduling using Dynamic Frequency Clocking. - Saraju P. Mohanty; N. Ranganathan; Vamsi Krishna (ISVLSI, 2002)

Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. - Sanjukta Bhanja; N. Ranganathan (ASP-DAC/VLSI Design, 2002)

A Real Delay Switching Activity Simulator Based on Petri Net Modeling. - Ashok K. Murugavel; N. Ranganathan (ASP-DAC/VLSI Design, 2002)

A comparative study of bidirectional ring and crossbar interconnection networks. - Hitoshi Oi; N. Ranganathan (Comput. Electr. Eng., 2002)

Least-square estimation of average power in digital CMOS circuits. - Ashok K. Murugavel; N. Ranganathan; Ramamurti Chandramouli; Srinath Chavali (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A low power scheduler using game theory. - N. Ranganathan; Ashok K. Murugavel (CODES+ISSS, 2003)

Simultaneous peak and average power minimization during datapath scheduling for DSP processors. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ACM Great Lakes Symposium on VLSI, 2003)

Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ICCD, 2003)

A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. - N. Ranganathan; Ashok K. Murugavel (ICCD, 2003)

Transient power minimization through datapath scheduling in multiple supply voltage environment. - Saraju P. Mohanty; Nagarajan Ranganathan; Sunil K. Chappidi (ICECS, 2003)

An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ISCAS (5), 2003)

Peak Power Minimization Through Datapath Scheduling. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ISVLSI, 2003)

Energy Efficient Scheduling for Datapath Synthesis. - Saraju P. Mohanty; N. Ranganathan (VLSI Design, 2003)

A Game-Theoretic Approach for Binding in Behavioral Synthesis. - Ashok K. Murugavel; N. Ranganathan (VLSI Design, 2003)

Switching activity estimation of VLSI circuits using Bayesian networks. - Sanjukta Bhanja; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Multiterminal net routing for partial crossbar-based multi-FPGA systems. - Abdel Ejnioui; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Routing on field-programmable switch matrices. - Abdel Ejnioui; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Petri net modeling of gate and interconnect delays for power estimation. - Ashok K. Murugavel; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A game theoretic approach for power optimization during behavioral synthesis. - Ashok K. Murugavel; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Control and Data Flow Graph Extraction for High-Level Synthesis. - Ravi Namballa; Nagarajan Ranganathan; Abdel Ejnioui (ISVLSI, 2004)

A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. - Narender Hanchate; Nagarajan Ranganathan (VLSI Design, 2004)

ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. - Saraju P. Mohanty; Nagarajan Ranganathan; Sunil K. Chappidi (VLSI Design, 2004)

VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. - Saraju P. Mohanty; Nagarajan Ranganathan; Ravi Namballa (VLSI Design, 2004)

Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. - Ashok K. Murugavel; N. Ranganathan (VLSI Design, 2004)

Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. - Ashok K. Murugavel; N. Ranganathan (VLSI Design, 2004)

Stochastic channel-adaptive rate control for wireless video transmission. - Ramamurti Chandramouli; Koduvayur P. Subbalakshmi; N. Ranganathan (Pattern Recognit. Lett., 2004)

Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. - Sanjukta Bhanja; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2004)

LECTOR: a technique for leakage reduction in CMOS circuits. - Narender Hanchate; Nagarajan Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A framework for energy and transient power reduction during behavioral synthesis. - Saraju P. Mohanty; Nagarajan Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Editorial. - N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. - Venkataraman Mahalingam; N. Ranganathan (ISVLSI, 2005)

Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. - Sanjukta Bhanja; Karthikeyan Lingasubramanian; N. Ranganathan (VLSI Design, 2005)

Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. - Saraju P. Mohanty; N. Ranganathan; Karthikeyan Balakrishnan (VLSI Design, 2005)

Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. - Saraju P. Mohanty; N. Ranganathan (ACM Trans. Design Autom. Electr. Syst., 2005)

A VLSI architecture for watermarking in a secure still digital camera (S2DC) design. - Saraju P. Mohanty; Nagarajan Ranganathan; Ravi Namballa (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A VLSI architecture for visible watermarking in a secure still digital camera (S2/DC) design (Corrected)*. - Saraju P. Mohanty; Nagarajan Ranganathan; Ravi Namballa (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A novel approach for variation aware power minimization during gate sizing. - Venkataraman Mahalingam; N. Ranganathan; Justin E. Harlow III (ISLPED, 2006)

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. - Narender Hanchate; Nagarajan Ranganathan (ISQED, 2006)

Social Fairness in Multi-Emergency Resource Management. - Upavan Gupta; N. Ranganathan (ISTAS, 2006)

CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. - Nagarajan Ranganathan; Ravi Namballa; Narender Hanchate (ISVLSI, 2006)

A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. - Narender Hanchate; Nagarajan Ranganathan (VLSI Design, 2006)

An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. - Venkataraman Mahalingam; N. Ranganathan (VLSI Design, 2006)

Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. - Aswath Oruganti; Nagarajan Ranganathan (VLSI Design, 2006)

An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. - Viswanath Sairaman; Nagarajan Ranganathan; Neeta S. Singh (VLSI Design, 2006)

Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. - Narender Hanchate; Nagarajan Ranganathan (IEEE Trans. Computers, 2006)

Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. - Venkataraman Mahalingam; Nagarajan Ranganathan (IEEE Trans. Computers, 2006)

A dual voltage-frequency VLSI chip for image watermarking in DCT domain. - Saraju P. Mohanty; Nagarajan Ranganathan; Karthikeyan Balakrishnan (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. - Sanjukta Bhanja; Karthikeyan Lingasubramanian; N. Ranganathan (ACM Trans. Design Autom. Electr. Syst., 2006)

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. - Narender Hanchate; Nagarajan Ranganathan (ACM Trans. Design Autom. Electr. Syst., 2006)

ILP models for simultaneous energy and transient power minimization during behavioral synthesis. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ACM Trans. Design Autom. Electr. Syst., 2006)

Improving the reliability of on-chip L2 cache using redundancy. - Koustav Bhattacharya; Soontae Kim; Nagarajan Ranganathan (ICCD, 2007)

A microeconomic approach to multi-robot team formation. - Upavan Gupta; Nagarajan Ranganathan (IROS, 2007)

Variation Aware Timing Based Placement Using Fuzzy Programming. - Venkataraman Mahalingam; N. Ranganathan (ISQED, 2007)

Integrated Gate and Wire Sizing at Post Layout Level. - Narender Hanchate; Nagarajan Ranganathan (ISVLSI, 2007)

Statistical Gate Sizing for Yield Enhancement at Post Layout Level. - Narender Hanchate; Nagarajan Ranganathan (ISVLSI, 2007)

A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. - Soumyaroop Roy; Srinivas Katkoori; Nagarajan Ranganathan (VLSI Design, 2007)

VLSI architecture and chip for combined invisible robust and fragile watermarking. - Saraju P. Mohanty; Elias Kougianos; Nagarajan Ranganathan (IET Comput. Digit. Tech., 2007)

A Sequential Distinguisher for Covert Channel Identification. - K. P. Subbalakshmi; Rajarathnam Chandramouli; Nagarajan Ranganathan (Int. J. Netw. Secur., 2007)

Multievent Crisis Management Using Noncooperative Multistep Games. - Upavan Gupta; Nagarajan Ranganathan (IEEE Trans. Computers, 2007)

A linear programming formulation for security-aware gate sizing. - Koustav Bhattacharya; Nagarajan Ranganathan (ACM Great Lakes Symposium on VLSI, 2008)

Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. - N. Ranganathan; Upavan Gupta; Venkataraman Mahalingam (ACM Great Lakes Symposium on VLSI, 2008)

A microeconomic approach to multi-objective spatial clustering. - Upavan Gupta; Nagarajan Ranganathan (ICPR, 2008)

Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. - Koustav Bhattacharya; Nagarajan Ranganathan (ISLPED, 2008)

An expected-utility based approach to variation aware VLSI optimization under scarce information. - Upavan Gupta; Nagarajan Ranganathan (ISLPED, 2008)

A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. - Venkataraman Mahalingam; Nagarajan Ranganathan (ISVLSI, 2008)

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. - Venkataraman Mahalingam; N. Ranganathan; J. E. Harlow (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Compiler-directed leakage reduction in embedded microprocessors. - Soumyaroop Roy; Nagarajan Ranganathan; Srinivas Katkoori (ICCD, 2009)

A VLSI System Architecture for Optical Flow Computation. - Koustav Bhattacharya; Venkataraman Mahalingam; Nagarajan Ranganathan (ISCAS, 2009)

A Strategy for Soft Error Reduction in Multi Core Designs. - Ransford Hyman Jr.; Koustav Bhattacharya; N. Ranganathan (ISCAS, 2009)

Exploring Compiler Optimizations for Enhancing Power Gating. - Soumyaroop Roy; Nagarajan Ranganathan; Srinivas Katkoori (ISCAS, 2009)

Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. - Himanshu Thapliyal; Nagarajan Ranganathan (ISCAS, 2009)

A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. - Koustav Bhattacharya; Nagarajan Ranganathan (ISQED, 2009)

A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. - Koustav Bhattacharya; Nagarajan Ranganathan (ISVLSI, 2009)

Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. - Himanshu Thapliyal; Nagarajan Ranganathan (ISVLSI, 2009)

RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. - Koustav Bhattacharya; Nagarajan Ranganathan (VLSI Design, 2009)

Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. - Himanshu Thapliyal; Nagarajan Ranganathan (VLSI Design, 2009)

Variation-aware multimetric optimization during gate sizing. - Nagarajan Ranganathan; Upavan Gupta; Venkataraman Mahalingam (ACM Trans. Design Autom. Electr. Syst., 2009)

A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. - Koustav Bhattacharya; Nagarajan Ranganathan; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A Framework for Power-Gating Functional Units in Embedded Microprocessors. - Soumyaroop Roy; Nagarajan Ranganathan; Srinivas Katkoori (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. - Himanshu Thapliyal; Nagarajan Ranganathan (VLSI Design, 2010)

Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. - Himanshu Thapliyal; Nagarajan Ranganathan (ACM J. Emerg. Technol. Comput. Syst., 2010)

A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets. - Upavan Gupta; Nagarajan Ranganathan (IEEE Trans. Knowl. Data Eng., 2010)

A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. - Venkataraman Mahalingam; Koustav Bhattacharya; N. Ranganathan; Hari Chakravarthula; Robin R. Murphy; Kevin S. Pratt (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Timing-Based Placement Considering Uncertainty Due to Process Variations. - Venkataraman Mahalingam; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2010)

An Instruction-Level Energy Estimation and Optimization Methodology for GPU. - Yue Wang; N. Ranganathan (CIT, 2011)

A new reversible design of BCD adder. - Himanshu Thapliyal; N. Ranganathan (DATE, 2011)

Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. - Matthew Morrison; Nagarajan Ranganathan (ISVLSI, 2011)

Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits - Himanshu Thapliyal; Nagarajan Ranganathan (CoRR, 2011)

Redundancy Mining for Soft Error Detection in Multicore Processors. - Ransford Hyman Jr.; Koustav Bhattacharya; Nagarajan Ranganathan (IEEE Trans. Computers, 2011)

State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores. - Soumyaroop Roy; Nagarajan Ranganathan; Srinivas Katkoori (IEEE Trans. Computers, 2011)

Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. - Koustav Bhattacharya; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization. - Upavan Gupta; Nagarajan Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Mach-Zehnder interferometer based design of all optical reversible binary adder. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (DATE, 2012)

Run-time power-gating in caches of GPUs for leakage energy savings. - Yue Wang; Soumyaroop Roy; Nagarajan Ranganathan (DATE, 2012)

Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (ISVLSI, 2012)

Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure. - Matthew Morrison; Matthew Lewandowski; Nagarajan Ranganathan (ISVLSI, 2012)

Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles. - Matthew Morrison; Nagarajan Ranganathan (ISVLSI, 2012)

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. - Himanshu Thapliyal; Nagarajan Ranganathan (ISVLSI, 2012)

Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. - Himanshu Thapliyal; Nagarajan Ranganathan (VLSI Design, 2012)

Dynamic clock stretching for variation compensation in VLSI circuit design. - Venkataraman Mahalingam; Nagarajan Ranganathan; Ransford Hyman Jr. (ACM J. Emerg. Technol. Comput. Syst., 2012)

Behavioral model of integrated qubit gates for quantum reversible logic design. - Matthew Lewandowski; Nagarajan Ranganathan; Matthew Morrison (ISVLSI, 2013)

A novel optimization method for reversible logic circuit minimization. - Matthew Morrison; Nagarajan Ranganathan (ISVLSI, 2013)

A new CRL gate as super class of Fredkin gate to design reversible quantum circuits. - Himanshu Thapliyal; Apeksha Bhatt; Nagarajan Ranganathan (MWSCAS, 2013)

Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits. - Sandip Kundu; Saraju P. Mohanty; Nagarajan Ranganathan (IET Circuits Devices Syst., 2013)

Design of efficient reversible logic-based binary and BCD adder circuits. - Himanshu Thapliyal; Nagarajan Ranganathan (ACM J. Emerg. Technol. Comput. Syst., 2013)

A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. - Ransford Hyman Jr.; Nagarajan Ranganathan; Thomas Bingel; Deanne Tran Vo (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Design of Testable Reversible Sequential Circuits. - Himanshu Thapliyal; Nagarajan Ranganathan; Saurabh Kotiyal (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures. - Yue Wang; Nagarajan Ranganathan (ISVLSI, 2014)

Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (VLSID, 2014)

Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS. - Matthew Morrison; Nagarajan Ranganathan (VLSID, 2014)

Efficient reversible NOR gates and their mapping in optical computing domain. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (Microelectron. J., 2014)

Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications. - Matthew Morrison; Nagarajan Ranganathan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (Trans. Comput. Sci., 2014)

Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits. - Himanshu Thapliyal; Nagarajan Ranganathan; Saurabh Kotiyal (Field-Coupled Nanocomputing, 2014)

A novel framework for mitigating insider attacks in big data systems. - Santosh Aditham; Nagarajan Ranganathan (IEEE BigData, 2015)

GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games. - Tony Casagrande; Nagarajan Ranganathan (DATE, 2015)

An energy-aware scheduling heuristic for distributed systems using non-cooperative games. - Santosh Aditham; Nagarajan Ranganathan (IGSC, 2015)

Reversible logic based multiplication computing unit using binary tree data structure. - Saurabh Kotiyal; Himanshu Thapliyal; Nagarajan Ranganathan (J. Supercomput., 2015)

Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits. - Matthew A. Morrison; Nagarajan Ranganathan; Jay Ligatti (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Memory access pattern based insider threat detection in big data systems. - Santosh Aditham; Nagarajan Ranganathan; Srinivas Katkoori (IEEE BigData, 2016)

A Novel Control-flow based Intrusion Detection Technique for Big Data Systems. - Santosh Aditham; Nagarajan Ranganathan (CoRR, 2016)

Call Trace and Memory Access Pattern based Runtime Insider Threat Detection for Big Data Platforms. - Santosh Aditham; Nagarajan Ranganathan; Srinivas Katkoori (CoRR, 2016)

Enabling New Computation Paradigms with HyperFET - An Emerging Device. - Wei-Yu Tsai; Xueqing Li 002; Matthew Jerry; Baihua Xie; Nikhil Shukla; Huichu Liu; Nandhini Chandramoorthy; Matthew Cotter; Arijit Raychowdhury; Donald M. Chiarulli; Steven P. Levitan; Suman Datta; et al. (IEEE Trans. Multi Scale Comput. Syst., 2016)

LSTM-Based Memory Profiling for Predicting Data Attacks in Distributed Big Data Systems. - Santosh Aditham; Nagarajan Ranganathan; Srinivas Katkoori (IPDPS Workshops, 2017)

A System Architecture for the Detection of Insider Attacks in Big Data Systems. - Santosh Aditham; Nagarajan Ranganathan (IEEE Trans. Dependable Secur. Comput., 2018)