OPSYN - OASYS Based Pseudosynthesis Tool. - N. S. Nagaraj (VLSI Design, 1992)

WCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits. - S. Nagaraj; N. Padmini; N. S. Nagaraj; R. Ramesh 001; V. Sachidanand (VLSI Design, 1992)

A New Optimizer for Performance Optimization of Analog Integrated Circuits. - N. S. Nagaraj (DAC, 1993)

A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing. - N. S. Nagaraj (ISCAS, 1993)

Approximate Computation of Signal Characteristics of On-chip RC Interconnect Trees. - N. S. Nagaraj; Paul Krivacek; Mark Harward (ISCAS, 1994)

Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century. - R. G. Bushroe; S. DasGupta; A. Dengi; P. Fisher; S. Grout; G. Ledenbach; N. S. Nagaraj; R. Steele (ISPD, 1997)

A Practical Approach to Static Signal Electromigration Analysis. - N. S. Nagaraj; Frank Cano; Haldun Haznedar; Duane Young (DAC, 1998)

Taming Noise in Deep Submicron Digital Integrated Circuits (Panel). - N. S. Nagaraj; Kenneth L. Shepard; Takahide Inone (DAC, 1998)

When bad things happen to good chips (panel session). - N. S. Nagaraj; Andrzej J. Strojwas; Sani R. Nassif; Ray Hokinson; Tak Young; Wonjae L. Kang; David Overhauser; Sung-Mo Kang (DAC, 2000)

Enabling DIR(Designing-In-Reliability) through CAD Capabilities. - Wonjae L. Kang; Brad Potts; Ray Hokinson; John Riley; David Doman; Frank Cano; N. S. Nagaraj; Noel Durrant (ISQED, 2000)

Full-Chip Signal Interconnect Analysis for Electromigration Reliability. - Steffen Rochel; N. S. Nagaraj (ISQED, 2000)

A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs. - N. S. Nagaraj; Frank Cano; Duane Young; Deepak Vohra; Manoj Das (VLSI Design, 2000)

Interconnect Modeling for Timing, Signal Integrity and Reliability. - Narain Arora; N. S. Nagaraj (ISQED, 2001)

Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. - N. S. Nagaraj; Poras T. Balsara; Cyrus D. Cantrell (ASP-DAC/VLSI Design, 2002)

A 600-MHz VLIW DSP. - Sanjive Agarwala; Timothy Anderson; Anthony M. Hill; M. D. Ales; Raguram Damodaran; Paul Wiley; Steven Mullinnix; J. Leach; Anthony Lell; Michael Gill; Arjun Rajagopal; Abhijeet Chachad; et al. (IEEE J. Solid State Circuits, 2002)

Benchmarks for Interconnect Parasitic Resistance and Capacitance. - N. S. Nagaraj; Tom Bonifield; Abha Singh; Frank Cano; Usha Narasimha; Mak Kulkarni; Poras T. Balsara; Cyrus D. Cantrell (ISQED, 2003)

Autonomic Incident Manager for Enterprise Applications. - Renuka Sindhgatta; Swaminathan Natarajan; Krishnakumar Pooloth; Colin Pinto; N. S. Nagaraj (GCC Workshops, 2004)

A 800 MHz System-on-Chip for Wireless Infrastructure Applications. - Sanjive Agarwala; Paul Wiley; Arjun Rajagopal; Anthony M. Hill; Raguram Damodaran; Lewis Nardini; Tim Anderson; Steven Mullinnix; Jose Flores; Heping Yue; Abhijeet Chachad; John Apostol; et al. (VLSI Design, 2004)

Interconnect Modeling for Copper/Low-k Technologies. - N. S. Nagaraj; Tom Bonifield; Abha Singh; Roger Griesmer; Poras T. Balsara (VLSI Design, 2004)

BEOL variability and impact on RC extraction. - N. S. Nagaraj; Tom Bonifield; Abha Singh; Clive Bittlestone; Usha Narasimha; Viet Le; Anthony M. Hill (DAC, 2005)

Dealing with interconnect process variations. - N. S. Nagaraj (SLIP, 2005)

The Impact of Inductance on Transients Affecting Gate Oxide Reliability. - N. S. Nagaraj; William R. Hunter; Poras T. Balsara; Cyrus D. Cantrell (VLSI Design, 2005)

Optimizing Interconnect for Performance in Standard Cell Library. - Dharin Shah; Kothamasu Siva; G. Girishankar; N. S. Nagaraj (APCCAS, 2006)

Statistical Analysis of Capacitance Coupling Effects on Delay and Noise. - Usha Narasimha; Binu Abraham; N. S. Nagaraj (ISQED, 2006)

Interconnect Process Variations: Theory and Practice. - N. S. Nagaraj (VLSI Design, 2006)

SmartExtract: Accurate Capacitance Extraction for SOC Designs. - Usha Narasimha; Anthony M. Hill; N. S. Nagaraj (VLSI Design, 2006)

DFM in practice: hit or hype? - Juan C. Rey; N. S. Nagaraj; Andrew B. Kahng; Fabian Klass; Rob Aitken; Cliff Hou; Luigi Capodieci; Vivek Singh (DAC, 2008)

Moore's Law: another casualty of the financial meltdown? - Jason Cong; N. S. Nagaraj; Ruchir Puri; William H. Joyner; Jeff Burns; Moshe Gavrielov; Riko Radojcic; Peter Rickert; Hans Stork (DAC, 2009)