Thermal aware test scheduling for stacked multi-chip-modules. - N. S. Vinay; Indira Rawat; Erik Larsson; Manoj Singh Gaur; Virendra Singh (EWDTS, 2010)

Physical-Design Aware Scan Cell Reordering for Low Power Testing. - Rohit Badjatya; N. S. Vinay; Rahul Kumar; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (EWDTS, 2024)