Covariance Based Steganography Using DCT. - N. Sathisha; K. Suresh Babu; K. B. Raja; K. R. Venugopal 001; Lalit M. Patnaik (ACC (2), 2011)

An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs. - Ankur Goel; Donald Evans; Richard Stephani; Venkateswara Reddy; Dharmendra Rai; Veerabadra Chary; N. Sathisha (VLSI Design, 2012)

DTCWT based high capacity steganography using coefficient replacement and adaptive scaling. - N. Sathisha; R. Priya; K. Suresh Babu; K. B. Raja; K. R. Venugopal 001; L. M. Patnaik (ICMV, 2013)

A robust 8T FinFET SRAM cell with improved stability for low voltage applications. - C. B. Kushwah; Devesh Dwivedi; N. Sathisha; Krishnan S. Rengarajan (VDAT, 2016)