Test generation for path-delay faults in one-dimensional iterative logic arrays. - Nabil M. Abdulrazzaq; Sandeep K. Gupta 001 (ITC, 2000)

Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. - Nabil M. Abdulrazzaq; Sandeep K. Gupta 001 (VTS, 2003)